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    Method to reduce breakdown failure in a MIM capacitor
    31.
    发明授权
    Method to reduce breakdown failure in a MIM capacitor 有权

    公开(公告)号：US11152455B2

    公开(公告)日：2021-10-19

    申请号：US16579738

    申请日：2019-09-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsing-Lien Lin ,  Chii-Ming Wu ,  Chia-Shiung Tsai ,  Chung-Yi Yu ,  Rei-Lin Chu

    IPC: H01L21/00 ,  H01L23/52 ,  H01L49/02 ,  H01L21/768 ,  H01L21/02 ,  H01L23/64 ,  H01L27/22

    Abstract: Various embodiments of the present application are directed towards a method for forming a metal-insulator-metal (MIM) capacitor comprising an enhanced interfacial layer to reduce breakdown failure. In some embodiments, a bottom electrode layer is deposited over a substrate. A native oxide layer is formed on a top surface of the bottom electrode layer and has a first adhesion strength with the top surface. A plasma treatment process is performed to replace the native oxide layer with an interfacial layer. The interfacial layer is conductive and has a second adhesion strength with the top surface of the bottom electrode layer, and the second adhesion strength is greater than the first adhesion strength. An insulator layer is deposited on the interfacial layer. A top electrode layer is deposited on the insulator layer. The top and bottom electrode layers, the insulator layer, and the interfacial layer are patterned to form a MIM capacitor.

    ROUGH BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON
    32.
    发明申请
    ROUGH BUFFER LAYER FOR GROUP III-V DEVICES ON SILICON 有权

    公开(公告)号：US20210273084A1

    公开(公告)日：2021-09-02

    申请号：US16806108

    申请日：2020-03-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuei-Ming Chen ,  Chi-Ming Chen ,  Chung-Yi Yu

    IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02

    Abstract: Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and/or a bottom surface of the rough buffer layer is/are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

    Semiconductor tool having controllable ambient environment processing zones
    33.
    发明授权
    Semiconductor tool having controllable ambient environment processing zones 有权

    公开(公告)号：US11047050B2

    公开(公告)日：2021-06-29

    申请号：US16352227

    申请日：2019-03-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chiao-Chun Hsu ,  Chih-Ming Chen ,  Chung-Yi Yu ,  Sheng-Hsun Lu

    IPC: H01L21/67 ,  C23C18/12 ,  H01L21/02

    Abstract: In some embodiments, a semiconductor fabrication tool is provided. The semiconductor fabrication tool includes a first processing zone having a first ambient environment and a second processing zone having a second ambient environment disposed at different location inside a processing chamber. A first exhaust port and a second exhaust port are disposed in the first and second processing zones, respectively. A first exhaust pipe couples the first exhaust port to a first individual exhaust output. A second exhaust pipe couples the second exhaust port to a second individual exhaust output, where the second exhaust pipe is separate from the first exhaust pipe. A first adjustable fluid control element controls the first ambient environment. A second adjustable fluid control element controls the second ambient environment, where the first adjustable fluid control element and the second adjustable fluid control element are independently adjustable.

    Capping structure to reduce dark current in image sensors
    34.
    发明授权
    Capping structure to reduce dark current in image sensors 有权

    公开(公告)号：US10861896B2

    公开(公告)日：2020-12-08

    申请号：US16047455

    申请日：2018-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Eugene Chen

    IPC: H01L27/146

    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.

    CAPPING STRUCTURE TO REDUCE DARK CURRENT IN IMAGE SENSORS
    36.
    发明申请
    CAPPING STRUCTURE TO REDUCE DARK CURRENT IN IMAGE SENSORS 审中-公开

    公开(公告)号：US20200035741A1

    公开(公告)日：2020-01-30

    申请号：US16047455

    申请日：2018-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Eugene Chen

    IPC: H01L27/146

    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure having a group IV chemical element disposed in a semiconductor substrate, where the epitaxial structure extends into the semiconductor substrate from a first side of the semiconductor substrate. A photodetector is at least partially arranged in the epitaxial structure. A first capping structure having a first capping structure chemical element that is different than the first group IV chemical element covers the epitaxial structure on the first side of the semiconductor substrate. A second capping structure is arranged between the first capping structure and the epitaxial structure, where the second capping structure includes the group IV chemical element and the first capping structure chemical element.

    High Electron Mobility Transistors
    37.
    发明申请
    High Electron Mobility Transistors 审中-公开

    公开(公告)号：US20190013399A1

    公开(公告)日：2019-01-10

    申请号：US16132793

    申请日：2018-09-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Po-Chun Liu ,  Chung-Yi Yu ,  Chi-Ming Chen ,  Chen-Hao Chiang

    IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/43 ,  H01L29/201

    Abstract: The present disclosure, in some embodiments, relates to a transistor device. The transistor device includes a layer of GaN over a substrate. A mobility-enhancing layer of AlzGa(1-z)N is over the layer of GaN and has a first molar fraction z in a first range of between approximately 0.25 and approximately 0.4. A resistance-reducing layer of AlxGa(1-x)N is over the mobility-enhancing layer and has a second molar fraction x in a second range of between approximately 0.1 and approximately 0.15. A source has a source contact and an underlying source region. A drain has a drain contact and an underlying drain region. The source and drain regions extend through the resistance-reducing layer of AlxGa(1-x)N and into the mobility-enhancing layer of AlzGa(1-z)N. The source and drain regions have bottoms over a bottom of the mobility-enhancing layer of AlzGa(1-z)N. A gate structure is laterally between the source and drain contacts.

    SEED LAYER STRUCTURE FOR GROWTH OF III-V MATERIALS ON SILICON
    40.
    发明申请
    SEED LAYER STRUCTURE FOR GROWTH OF III-V MATERIALS ON SILICON 有权
    用于在硅上生长III-V材料的种子层结构

    公开(公告)号：US20160322225A1

    公开(公告)日：2016-11-03

    申请号：US14699046

    申请日：2015-04-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Ming Chen ,  Chung-Yi Yu ,  Po-Chun Liu

    IPC: H01L21/02 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66

    CPC classification number: H01L21/02694 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/02617 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

    Abstract: The present disclosure relates to a structure and method of forming a GaN film on a Si substrate that includes an additional or second high temperature (HT) AlN seed layer, introduced for reducing the tensile stress of GaN on a Si substrate. The second HT AlN seed layer is disposed over a first HT AlN seed layer, and has a low V/III ratio compared to the first HT AlN seed layer. The second HT AlN seed layer has better lattice matching between Si and GaN and this reduces the tensile stress on GaN. The additional HT AlN seed layer further acts as a capping layer and helps annihilate or terminate threading dislocations (TDs) originating from a LT AlN seed layer. The second HT AlN seed layer also helps prevent Si diffusion from the substrate to the GaN film.

    Abstract translation: 本公开内容涉及在Si衬底上形成GaN膜的结构和方法，该衬底包括用于降低Si衬底上GaN的拉伸应力的额外的或第二高温（HT）AlN晶种层。 第二HT AlN种子层设置在第一HT AlN籽晶层上，并且与第一HT AlN种子层相比具有低的V / III比。 第二个HT AlN种子层在Si和GaN之间具有更好的晶格匹配，并且这降低了GaN上的拉伸应力。 附加的HT AlN种子层还起到盖层的作用，并有助于消除或终止来自LT AlN种子层的穿透位错（TD）。 第二HT AlN种子层还有助于防止Si从衬底扩散到GaN膜。

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