公开(公告)号：US20220059759A1

公开(公告)日：2022-02-24

申请号：US16998911

申请日：2020-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: A method for manufacturing a memory device includes forming a via trench in a substrate and forming a via in the via trench. A lower portion of the via includes a first metal and an upper portion of the via includes a second metal that is different from the first metal. The method further includes forming a magnetic tunneling junction over the via and forming a top electrode over the magnetic tunneling junction.

公开(公告)号：US11222857B2

公开(公告)日：2022-01-11

申请号：US16798749

申请日：2020-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Dian-Hau Chen ,  Mao-Nan Wang ,  Tzu-Li Lee ,  Yen-Ming Chen ,  Tzung-Luen Li

IPC: H01L23/498 ,  H01L23/00

Abstract: In some embodiments, the present disclosure relates to a method including forming an interconnect structure over a substrate. A bond pad may be coupled to the interconnect structure, and a polymeric material may be deposited over the bond pad. In some embodiments, the method further includes performing a patterning process to remove a portion of the polymeric material to form an opening in the polymeric material. The opening directly overlies and exposes the bond pad. Further, the method includes a first cleaning process. The polymeric material is cured to form a polymeric protection layer, and a second cleaning process is performed.

公开(公告)号：US11189538B2

公开(公告)日：2021-11-30

申请号：US16411529

申请日：2019-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Mao-Nan Wang ,  Kuo-Chin Chang ,  Hui-Chi Chen ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/522 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56 ,  H01L21/768

Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.

公开(公告)号：US20210098399A1

公开(公告)日：2021-04-01

申请号：US16936910

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Chih-Sheng Li ,  Chih-Hung Lu ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L21/02

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method includes depositing a first dielectric layer over a metal pad disposed over a workpiece, forming a first opening in the first dielectric layer to expose a portion of the metal pad, after the forming of the first opening, forming a second dielectric layer over the exposed portion of the metal pad, depositing a first polymeric material over the second dielectric layer, forming a second opening through the first polymeric material and the second dielectric layer to expose the metal pad, and forming a bump feature over the exposed metal pad.

公开(公告)号：US20200168574A1

公开(公告)日：2020-05-28

申请号：US16392024

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hui-Chi Chen ,  Kuo-Chin Chang ,  Chien-Huang Yeh ,  Hong-Seng Shue ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L23/00 ,  H01L23/522

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

公开(公告)号：US09852992B2

公开(公告)日：2017-12-26

申请号：US15484344

申请日：2017-04-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey Wu ,  Dian-Hau Chen ,  Jye-Yen Cheng ,  Sheng-Hsuan Wei ,  Li-Yu Lee ,  TaiYang Wu

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/033

CPC classification number: H01L23/5329 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

公开(公告)号：US20250070064A1

公开(公告)日：2025-02-27

申请号：US18403064

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ke-Gang Wen ,  Yu-Bey Wu ,  Liang-Wei Wang ,  Hsin-Feng Chen ,  Tsung-Chieh Hsiao ,  Chih Chuan Su ,  Dian-Hau Chen

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.

公开(公告)号：US20250046667A1

公开(公告)日：2025-02-06

申请号：US18482217

申请日：2023-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Chieh Hsiao ,  Ke-Gang Wen ,  Chih-Pin Chiu ,  Hsin-Feng Chen ,  Yu-Bey Wu ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/065

Abstract: A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.

公开(公告)号：US20240355766A1

公开(公告)日：2024-10-24

申请号：US18448407

申请日：2023-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Pin Chiu ,  Yu-Bey Wu ,  Dian-Hau Chen

IPC: H01L23/00 ,  H01L23/485

CPC classification number: H01L24/06 ,  H01L23/485 ,  H01L24/03 ,  H01L2224/03005 ,  H01L2224/06102

Abstract: A first bond pad of a first device and a second bond pad of a second device are implanted with metal ions. The first and second semiconductor device are bonded together using a direct metal-to-metal bond and an overlay offset occurs between the bond pads such that a portion of the first bond pad and a portion of the second bond pad overlaps and contacts a dielectric material layer. During the bonding process, however, diffusion of the metal ions provides a barrier layer at the interface of the bond pads and the dielectric layers.

公开(公告)号：US20240128312A1

公开(公告)日：2024-04-18

申请号：US18395110

申请日：2023-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Dian-Hau Chen

IPC: H01G4/30

CPC classification number: H01L28/91 ,  H01L28/40 ,  H01L28/60 ,  H01L28/75 ,  H01L28/86 ,  H01L28/90

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a contact feature in a first dielectric layer, a first passivation layer over the contact feature, a bottom conductor plate layer disposed over the first passivation layer and including a first plurality of sublayers, a second dielectric layer over the bottom conductor plate layer, a middle conductor plate layer disposed over the second dielectric layer and including a second plurality of sublayers, a third dielectric layer over the middle conductor plate layer, a top conductor plate layer disposed over the third dielectric layer and including a third plurality of sublayers, and a second passivation layer over the top conductor plate layer.