公开(公告)号：US20230369380A1

公开(公告)日：2023-11-16

申请号：US17740544

申请日：2022-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Y.C. Chang ,  Yen-Ting Chiang ,  Shyh-Fann Ting ,  Jen-Cheng Liu

IPC: H01L27/146

CPC classification number: H01L27/14683 ,  H01L27/14643 ,  H01L27/14627 ,  H01L27/14621 ,  H01L27/14636

Abstract: The present disclosure describes an image sensor and a method for forming the image sensor. The image sensor includes an image sensing element disposed on a substrate, an extension pad disposed adjacent to the image sensing element, and a polysilicon pillar disposed on the extension pad. The image sensor further includes an insulating layer disposed over the image sensing element, the extension pad, and the polysilicon pillar.

公开(公告)号：US11791332B2

公开(公告)日：2023-10-17

申请号：US17371660

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin

IPC: H01L21/00 ,  H01L27/06 ,  H01L49/02 ,  H01L29/861 ,  H01L23/00 ,  H01L29/66 ,  H01L21/265 ,  H01L23/522

CPC classification number: H01L27/0676 ,  H01L21/26513 ,  H01L23/5226 ,  H01L24/08 ,  H01L28/40 ,  H01L29/66136 ,  H01L29/861 ,  H01L2224/08145

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

公开(公告)号：US20230317758A1

公开(公告)日：2023-10-05

申请号：US17879556

申请日：2022-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ying Ho ,  Kuan-Hua Lin ,  Keng-Yu Chou ,  Kai-Chun Hsu ,  Sung-En Lin ,  Wen-De Wang ,  Jen-Cheng Liu

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14645 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14685

Abstract: An optical device with isolation structures and a method of fabricating the same are disclosed. The optical device includes a substrate having a first surface and a second surface opposite to the first surface, first and second radiation sensing devices disposed in the substrate, a first isolation structure disposed in the substrate. The first isolation structure has a first surface and a second surface opposite to the first surface. The optical device further includes a second isolation structure disposed in the substrate and on the first surface of the first isolation structure. The second isolation structure includes a metal structure and a dielectric layer surrounding the metal structure. The second isolation structure vertically extends over the first surface of the substrate.

公开(公告)号：US11495630B2

公开(公告)日：2022-11-08

申请号：US16924579

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Chuang Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Jen-Cheng Liu ,  Yen-Ting Chiang ,  Chun-Yuan Chen ,  Shen-Hui Hong

IPC: H01L27/146 ,  H04N5/374 ,  H04N5/369

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a plurality of pixel regions disposed within a substrate and respectively comprising a photodiode configured to receive radiation that enters the substrate from a back-side. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions surrounding the photodiode. The BDTI structure extends from the back-side of the substrate to a first depth within the substrate. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel regions overlying the photodiode. The MDTI structure extends from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure is a continuous integral unit having a ring shape.

公开(公告)号：US20220310507A1

公开(公告)日：2022-09-29

申请号：US17352969

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin ,  Kuan-Hua Lin

IPC: H01L23/522 ,  H01L49/02

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

公开(公告)号：US20220278095A1

公开(公告)日：2022-09-01

申请号：US17371660

申请日：2021-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsing-Chih Lin

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/861 ,  H01L23/522 ,  H01L23/00 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first substrate, a capacitor within the first substrate, a diode structure within the first substrate adjacent the capacitor, and a first interconnect structure over the capacitor and the diode structure. A first conductive via of the first interconnect structure electrically couples the capacitor to the diode structure.

公开(公告)号：US11410972B2

公开(公告)日：2022-08-09

申请号：US16896348

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00

Abstract: A method for manufacturing three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is formed and bonded to a first IC die by a first bonding structure. A third IC die is formed and bonded to the second IC die by a second bonding structure. The second bonding structure is formed between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. In some further embodiments, the second bonding structure is formed by forming conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

公开(公告)号：US20220238568A1

公开(公告)日：2022-07-28

申请号：US17336852

申请日：2021-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-Chang Kuo ,  Sheng-Chau Chen ,  Feng-Chi Hung ,  Sheng-Chan Li

IPC: H01L27/146

Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.

公开(公告)号：US20220208749A1

公开(公告)日：2022-06-30

申请号：US17696565

申请日：2022-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Ting Tsai ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Szu-Ying Chen ,  U-Ting Chen

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L23/00

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive feature formed over the second substrate. A conductive plug is disposed through the first conductive feature and is coupled to the second conductive feature. The conductive plug includes a first portion disposed over the first conductive feature, the first portion having a first width, and a second portion disposed beneath or within the first conductive feature. The second portion has a second width. The first width is greater than the second width.

公开(公告)号：US11282769B2

公开(公告)日：2022-03-22

申请号：US16898647

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen

IPC: H01L29/40 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a standard via disposed on a first side of a substrate. An oversized via is disposed on the first side of the substrate and is laterally separated from the standard via. The oversized via has a larger width than the standard via. An interconnect wire vertically contacting the oversized via. A through-substrate via (TSV) extends from a second side of the substrate, and through the substrate, to physically contact the oversized via or the interconnect wire. The TSV has a minimum width that is smaller than a width of the oversized via.