公开(公告)号：US20240186412A1

公开(公告)日：2024-06-06

申请号：US18441118

申请日：2024-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu Chen ,  Wan-Hua Huang ,  Jing-Ying Chen ,  Kuo-Ming Wu

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/0653 ,  H01L29/1087 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

公开(公告)号：US20230282525A1

公开(公告)日：2023-09-07

申请号：US17748363

申请日：2022-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hong-Shyang Wu ,  Kuo-Ming Wu

IPC: H01L21/8258 ,  H01L27/12 ,  H01L23/535 ,  H01L21/84

CPC classification number: H01L21/8258 ,  H01L27/1207 ,  H01L27/1203 ,  H01L23/535 ,  H01L21/84 ,  H01L21/76251

Abstract: In an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.

公开(公告)号：US20220362903A1

公开(公告)日：2022-11-17

申请号：US17317968

申请日：2021-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Lung Lin ,  Kuo-Ming Wu ,  Cheng-Hsien Chou ,  I-Nan Chen ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai

IPC: B24B37/14 ,  B24B37/10

Abstract: Various embodiments of the present disclosure are directed towards a chemical mechanical polishing (CMP) system including a first CMP head and a second CMP head. The first CMP head is configured to retain a workpiece and comprises a first plurality of pressure elements disposed across a first pressure control plate. The second CMP head is configured to retain the workpiece. The second CMP head comprises a second plurality of pressure elements disposed across a second pressure control plate. A distribution of the first plurality of pressure elements across the first pressure control plate is different from a distribution of the second plurality of pressure elements across the second pressure control plate.

公开(公告)号：US11322481B2

公开(公告)日：2022-05-03

申请号：US16902539

申请日：2020-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ming Wu ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Min-Feng Kao ,  Yung-Lung Lin ,  Shih-Han Huang ,  I-Nan Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/48 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00

Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. A third IC die is bonded to the second IC die by a second bonding structure. The second bonding structure is arranged between back sides of the second IC die and the third IC die opposite to corresponding interconnect structures and comprises a first TSV (through substrate via) disposed through a second substrate of the second IC die and a second TSV disposed through a third substrate of the third IC die. The second bonding structure further comprises conductive features with oppositely titled sidewalls disposed between the first TSV and the second TSV.

公开(公告)号：US20200321251A1

公开(公告)日：2020-10-08

申请号：US16908966

申请日：2020-06-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Chih-Hui Huang ,  Kuo-Ming Wu

IPC: H01L21/822 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.

公开(公告)号：US10679987B2

公开(公告)日：2020-06-09

申请号：US16128578

申请日：2018-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chiu-Hua Chung ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Tien Sheng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L29/06 ,  H01L27/07 ,  H01L21/8234 ,  H01L21/761 ,  H01L29/78 ,  H01L27/06 ,  H01L29/861

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.

公开(公告)号：US20200075657A1

公开(公告)日：2020-03-05

申请号：US16121958

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hui Huang ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Kuo-Ming Wu ,  Sheng-Chan Li

IPC: H01L27/146

Abstract: Various embodiments of the present application are directed towards an image sensor having a reflector. In some embodiments, the image sensor comprises a substrate, an interlayer dielectric (ILD) structure, an etch stop layer, a wire, and the reflector. The substrate comprises a photodetector. The ILD structure is over the substrate, and the etch stop layer is over the ILD structure. The wire is in the etch stop layer. The reflector is directly over the photodetector and is in the etch stop layer. An upper surface of the wire is elevated above an upper surface of the reflector. By forming the reflector directly over the photodetector, the reflector may reflect radiation that passes through the photodetector without being absorbed back to the photodetector. This gives the photodetector a second chance to absorb the radiation and enhances the quantum efficiency (QE) of the photodetector.

公开(公告)号：US10297661B2

公开(公告)日：2019-05-21

申请号：US15694341

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Chiu ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Karthick Murukesan

IPC: H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

Abstract: The present disclosure relates to a high voltage resistor device that is able to receive high voltages using a small footprint, and an associated method of fabrication. In some embodiments, the high voltage resistor device has a substrate including a first region with a first doping type, and a drift region arranged within the substrate over the first region and having a second doping type. A body region having the first doping type laterally contacts the drift region. A drain region having the second doping type is arranged within the drift region, and an isolation structure is over the substrate between the drain region and the body region. A resistor structure is over the isolation structure and has a high-voltage terminal coupled to the drain region and a low-voltage terminal coupled to a gate structure over the isolation structure.

公开(公告)号：US20190131296A1

公开(公告)日：2019-05-02

申请号：US16128578

申请日：2018-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chiu-Hua Chung ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Tien Sheng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L27/07 ,  H01L21/8234

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.

公开(公告)号：US09281331B2

公开(公告)日：2016-03-08

申请号：US14308910

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chau Chen ,  Chih-Yu Lai ,  Kuo-Ming Wu ,  Kuo-Hwa Tzeng ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC: H01L31/062 ,  H01L27/146 ,  H01L29/51 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L27/14614 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66621

Abstract: A vertical-gate transfer transistor of an active pixel sensor (APS) is provided. The transistor includes a semiconductor substrate, a vertical trench extending into the semiconductor substrate, a dielectric lining the vertical trench, and a vertical gate filling the lined vertical trench. The dielectric includes a dielectric constant exceeding 3.9 (i.e., the dielectric constant of silicon dioxide). A method of manufacturing the vertical-gate transfer transistor, an APS including the vertical-gate transfer transistor, a method of manufacturing the APS, and an image sensor including a plurality of the APSs are also provided.

Abstract translation: 提供了一种有源像素传感器（APS）的垂直栅极传输晶体管。 晶体管包括半导体衬底，延伸到半导体衬底中的垂直沟槽，垂直沟槽的电介质衬里，以及填充衬里垂直沟槽的垂直栅极。 电介质包括超过3.9的介电常数（即二氧化硅的介电常数）。 还提供了制造垂直栅极转移晶体管的方法，包括垂直栅极转移晶体管的APS，制造APS的方法以及包括多个APS的图像传感器。