公开(公告)号：US10468410B2

公开(公告)日：2019-11-05

申请号：US15989648

申请日：2018-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L21/762 ,  H01L29/40

Abstract: In some embodiments, the present disclosure, relates to an integrated chip. The integrated chip has an isolation structure arranged within a substrate. The isolation structure has interior surfaces defining one or more divots recessed below an uppermost surface of the isolation structure and sidewalls defining an opening exposing the substrate. A source region is disposed within the opening. A drain region is also disposed within the opening and is separated from the source region by a channel region along a first direction. A gate structure extends over the channel region. The gate structure includes a first gate electrode region having a first composition of one or more materials and a second gate electrode region disposed over the one or more divots and having a second composition of one or more materials different than the first composition of one or more materials.

公开(公告)号：US20190088561A1

公开(公告)日：2019-03-21

申请号：US15962177

申请日：2018-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Ya-Chen Kao ,  Chen-Chin Liu ,  Chih-Pin Huang

IPC: H01L21/66 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11529

CPC classification number: H01L22/34 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42328

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

公开(公告)号：US10049939B2

公开(公告)日：2018-08-14

申请号：US15216569

申请日：2016-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu

IPC: H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.

公开(公告)号：US09831134B1

公开(公告)日：2017-11-28

申请号：US15278812

申请日：2016-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Chih-Ren Hsieh ,  Chen-Chin Liu

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/266 ,  H01L21/762 ,  H01L21/761

CPC classification number: H01L21/823892 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0928

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US20240389334A1

公开(公告)日：2024-11-21

申请号：US18785757

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C11/22 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H10B43/20 ,  H10B43/27 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US20240284679A1

公开(公告)日：2024-08-22

申请号：US18631842

申请日：2024-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C5/06 ,  G11C11/22 ,  H01L21/822 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B51/20 ,  G11C5/06 ,  G11C11/223 ,  H01L21/8221 ,  H01L29/6684 ,  H01L29/78391

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

公开(公告)号：US12027412B2

公开(公告)日：2024-07-02

申请号：US17814626

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L21/762 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

CPC classification number: H01L21/76237 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric material.

公开(公告)号：US20240164109A1

公开(公告)日：2024-05-16

申请号：US18406745

申请日：2024-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  H01L23/535 ,  H01L29/417 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  H01L23/535 ,  H01L29/41741 ,  H01L29/41775 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

公开(公告)号：US11985830B2

公开(公告)日：2024-05-14

申请号：US17874908

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Cheng Yang ,  Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C5/06 ,  G11C11/22 ,  H01L21/822 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B51/20 ,  G11C5/06 ,  G11C11/223 ,  H01L21/8221 ,  H01L29/6684 ,  H01L29/78391

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.

公开(公告)号：US11923427B2

公开(公告)日：2024-03-05

申请号：US17185915

申请日：2021-02-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Wei-Cheng Wu ,  Te-Hsin Chiu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L29/42368 ,  H01L21/02244 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.