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31.
公开(公告)号:US20210125907A1
公开(公告)日:2021-04-29
申请号:US16798404
申请日:2020-02-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Kuan-Yu Huang , Sung-Hui Huang , Shang-Yun Hou
IPC: H01L23/498 , H01L23/00 , H01L23/053 , H01L21/48
Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, connective terminals and supports. The circuit substrate has a first side and a second side opposite to the first side. The semiconductor package is connected to the first side of the circuit substrate. The connective terminals are located on the second side of the circuit substrate and are electrically connected to the semiconductor package via the circuit substrate. The supports are located on the second side of the circuit substrate beside the connective terminals. A material of the supports has a melting temperature higher than a melting temperature of the connective terminals.
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公开(公告)号:US20210088723A1
公开(公告)日:2021-03-25
申请号:US16930558
申请日:2020-07-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chen-Hua Yu , Hsing-Kuo Hsia , Kuo-Chiang Ting , Sung-Hui Huang , Shang-Yun Hou , Chi-Hsi Wu
IPC: G02B6/122
Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.
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公开(公告)号:US10886147B1
公开(公告)日:2021-01-05
申请号:US16571786
申请日:2019-09-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Kuan-Yu Huang , Sung-Hui Huang , Shang-Yun Hou
Abstract: A method for forming the package structure is provided. The method includes forming a die structure over a first surface of a first substrate, and forming a plurality of electrical connectors below a second surface of the first substrate. The method also includes forming a first protruding structure below the second surface of the first substrate, and the electrical connectors are surrounded by the first protruding structure. The method further includes forming a second protruding structure over a second substrate, and bonding the first substrate to the second substrate. The electrical connectors are surrounded by the second protruding structure, and the first protruding structure does not overlap with the second protruding structure.
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公开(公告)号:US12253729B2
公开(公告)日:2025-03-18
申请号:US17952681
申请日:2022-09-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chen-Hua Yu , Hsing-Kuo Hsia , Sung-Hui Huang , Kuan-Yu Huang , Kuo-Chiang Ting , Shang-Yun Hou , Chi-Hsi Wu
Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.
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公开(公告)号:US12242108B2
公开(公告)日:2025-03-04
申请号:US18526706
申请日:2023-12-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chen-Hua Yu , Hsing-Kuo Hsia , Kuo-Chiang Ting , Sung-Hui Huang , Shang-Yun Hou , Chi-Hsi Wu
Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.
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公开(公告)号:US12237288B2
公开(公告)日:2025-02-25
申请号:US18446732
申请日:2023-08-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Kuan-Yu Huang , Sung-Hui Huang , Shang-Yun Hou , Shu Chia Hsu , Yu-Yun Huang , Wen-Yao Chang , Yu-Jen Cheng
IPC: H01L23/00 , H01L21/48 , H01L21/56 , H01L21/683 , H01L23/31 , H01L23/498 , H01L25/00 , H01L25/065
Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.
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公开(公告)号:US20240297166A1
公开(公告)日:2024-09-05
申请号:US18664483
申请日:2024-05-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Shang-Yun Hou , Sung-Hui Huang , Kuan-Yu Huang , Hsien-Pin Hu , Yushun Lin , Heh-Chang Huang , Hsing-Kuo Hsia , Chih-Chieh Hung , Ying-Ching Shih , Chin-Fu Kao , Wen-Hsin Wei , Li-Chung Kuo , Chi-Hsi Wu , Chen-Hua Yu
IPC: H01L25/00 , H01L21/48 , H01L23/00 , H01L23/24 , H01L23/31 , H01L23/498 , H01L25/065 , H01L25/18
CPC classification number: H01L25/50 , H01L21/4803 , H01L21/4853 , H01L23/24 , H01L23/3128 , H01L23/49827 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L2224/0401 , H01L2224/1144 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/16145 , H01L2224/16227 , H01L2224/16235 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81191 , H01L2224/81815 , H01L2224/92125 , H01L2224/92225 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/14 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/1461 , H01L2924/15311 , H01L2924/18161
Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
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公开(公告)号:US12051668B2
公开(公告)日:2024-07-30
申请号:US18324514
申请日:2023-05-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Kuan-Yu Huang , Li-Chung Kuo , Sung-Hui Huang , Shang-Yun Hou , Tsung-Yu Chen , Chien-Yuan Huang
IPC: H01L23/00 , H01L21/60 , H01L23/32 , H01L25/065
CPC classification number: H01L24/27 , H01L23/32 , H01L24/94 , H01L24/95 , H01L25/0657 , H01L2021/60097
Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.
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公开(公告)号:US20240103220A1
公开(公告)日:2024-03-28
申请号:US18526706
申请日:2023-12-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chen-Hua Yu , Hsing-Kuo Hsia , Kuo-Chiang Ting , Sung-Hui Huang , Shang-Yun Hou , Chi-Hsi Wu
IPC: G02B6/122
CPC classification number: G02B6/1225 , G02B6/12019
Abstract: A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.
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公开(公告)号:US11694939B2
公开(公告)日:2023-07-04
申请号:US16881004
申请日:2020-05-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Sung-Hui Huang , Shang-Yun Hou , Tien-Yu Huang , Heh-Chang Huang , Kuan-Yu Huang , Shu-Chia Hsu , Yu-Shun Lin
CPC classification number: H01L23/3185 , H01L25/167
Abstract: A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.
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