公开(公告)号：US10141281B2

公开(公告)日：2018-11-27

申请号：US15242722

申请日：2016-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hung Lin ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Yu-Min Liang ,  Chen-Shien Chen ,  Chung-Shi Liu

IPC: H01L23/00

Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

公开(公告)号：US12142560B2

公开(公告)日：2024-11-12

申请号：US17408840

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shi Liu ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Hao-Cheng Hou ,  Hung-Jen Lin ,  Jung Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Li-Wei Chou

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

公开(公告)号：US12080563B2

公开(公告)日：2024-09-03

申请号：US17994841

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L21/486 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/5226

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US11894312B2

公开(公告)日：2024-02-06

申请号：US17869286

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chun-Chih Chuang ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Jiun Yi Wu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19106

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

公开(公告)号：US20240038646A1

公开(公告)日：2024-02-01

申请号：US17878647

申请日：2022-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Hao-Cheng Hou ,  Jung Wei Cheng ,  Yu-Min Liang ,  Tsung-Ding Wang

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/14

CPC classification number: H01L23/49816 ,  H01L24/73 ,  H01L24/32 ,  H01L24/16 ,  H01L25/0655 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/145 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/182 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2224/16235 ,  H01L21/486

Abstract: Semiconductor device packages and methods of forming the same are discussed. In an embodiment, a device includes: a redistribution structure comprising an upper dielectric layer and an under-bump metallization; a buffer feature on the under-bump metallization and the upper dielectric layer, the buffer feature covering an edge of the under-bump metallization, the buffer feature bonded to the upper dielectric layer; a reflowable connector extending through the buffer feature, the reflowable connector coupled to the under-bump metallization; an interposer coupled to the reflowable connector; and an encapsulant around the interposer and the reflowable connector, the encapsulant different from the buffer feature.

公开(公告)号：US20230091737A1

公开(公告)日：2023-03-23

申请号：US17994841

申请日：2022-11-28

Applicant: Taiwan Semiconductor Manufacturing Co.,Ltd.

Inventor： Chien-Hsun Chen ,  Yu-Min Liang ,  Yen-Ping Wang ,  Jiun Yi Wu ,  Chen-Hua Yu ,  Kai-Chiang Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/522 ,  H01L23/31 ,  H01L23/48 ,  H01L21/768

Abstract: Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

公开(公告)号：US10790210B2

公开(公告)日：2020-09-29

申请号：US16171326

申请日：2018-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chien-Hsun Lee ,  Yu-Min Liang

IPC: H01L21/44 ,  H01L23/24 ,  H01L23/00 ,  H01L23/433 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56

Abstract: A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure.

公开(公告)号：US10700031B2

公开(公告)日：2020-06-30

申请号：US16215679

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Hai-Ming Chen ,  Kuan-Lin Ho ,  Yu-Min Liang

IPC: H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L21/683

Abstract: An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a seed layer, conductive pillars, and a buffer layer. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure includes dielectric layers and conductive patterns. The dielectric layers are sequentially stacked and the conductive patterns are sandwiched between the dielectric layers. The seed layer and the conductive pillars are sequentially stacked over the redistribution structure. The seed layer is directly in contact with the conductive patterns closest to the conductive pillars. The buffer layer is disposed over the redistribution structure. The dielectric layer closest to the conductive pillars and the buffer layer are sandwiched between the seed layer and the conductive patterns closest to the conductive pillars. A Young's modulus of the buffer layer is higher than a Young's modulus of each of the dielectric layers of the redistribution structure.

公开(公告)号：US10658263B2

公开(公告)日：2020-05-19

申请号：US15993615

申请日：2018-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Wen-Lin Chen

IPC: H01L23/34 ,  H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.

公开(公告)号：US20190131262A1

公开(公告)日：2019-05-02

申请号：US16215679

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chin-Liang Chen ,  Hai-Ming Chen ,  Kuan-Lin Ho ,  Yu-Min Liang

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L21/56 ,  H01L23/532 ,  H01L23/522

Abstract: An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a seed layer, conductive pillars, and a buffer layer. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure includes dielectric layers and conductive patterns. The dielectric layers are sequentially stacked and the conductive patterns are sandwiched between the dielectric layers. The seed layer and the conductive pillars are sequentially stacked over the redistribution structure. The seed layer is directly in contact with the conductive patterns closest to the conductive pillars. The buffer layer is disposed over the redistribution structure. The dielectric layer closest to the conductive pillars and the buffer layer are sandwiched between the seed layer and the conductive patterns closest to the conductive pillars. A Young's modulus of the buffer layer is higher than a Young's modulus of each of the dielectric layers of the redistribution structure.