公开(公告)号：US20120181630A1

公开(公告)日：2012-07-19

申请号：US13006656

申请日：2011-01-14

申请人： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

发明人： Takashi Ando ,  Michael P. Chudzik ,  Rishikesh Krishnan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28008 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7843

摘要： Replacement gate work function material stacks are provided, which provides a work function about the energy level of the conduction band of silicon. After removal of a disposable gate stack, a gate dielectric layer is formed in a gate cavity. A metallic compound layer including a metal and a non-metal element is deposited directly on the gate dielectric layer. At least one barrier layer and a conductive material layer is deposited and planarized to fill the gate cavity. The metallic compound layer includes a material having a work function about 4.4 eV or less, and can include a material selected from tantalum carbide and a hafnium-silicon alloy. Thus, the metallic compound layer can provide a work function that enhances the performance of an n-type field effect transistor employing a silicon channel.

摘要翻译： 提供了替代栅极工作功能材料堆叠，其提供关于硅导带的能级的功函数。 在去除一次性栅极堆叠之后，在栅极腔中形成栅极电介质层。 包括金属和非金属元素的金属化合物层直接沉积在栅极介电层上。 沉积至少一个势垒层和导电材料层并平坦化以填充栅极腔。 金属化合物层包括功函数约4.4eV或更低的材料，并且可以包括选自碳化钽和铪硅合金的材料。 因此，金属化合物层可以提供增强采用硅通道的n型场效应晶体管的性能的功函数。

公开(公告)号：US20120147241A1

公开(公告)日：2012-06-14

申请号：US13402298

申请日：2012-02-22

申请人： Tetsuji Yamaguchi ,  Yasushi Maruyama ,  Takashi Ando ,  Susumu Hiyama ,  Yuko Ohgishi

发明人： Tetsuji Yamaguchi ,  Yasushi Maruyama ,  Takashi Ando ,  Susumu Hiyama ,  Yuko Ohgishi

IPC分类号： H04N5/335 ,  H01L27/148

CPC分类号： H01L27/14609 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14685 ,  H01L31/022466 ,  H01L31/022475

摘要： A solid-state imaging device includes a substrate with oppositely facing first surface and second surfaces, light being received through the second surface; a wiring layer on the first surface; a photodetector in the substrate; a charge accummulation region between the second surface and the photodetector; and an insulating layer over the second surface, the insulating layer have a region that is at least partially crystallized.

摘要翻译： 固态成像装置包括具有相对面对的第一表面和第二表面的基板，光被接收通过第二表面; 第一表面上的布线层; 基板上的光电检测器; 所述第二表面和所述光电检测器之间的电荷累积区域; 以及在所述第二表面上的绝缘层，所述绝缘层具有至少部分地结晶的区域。

公开(公告)号：US20120083121A1

公开(公告)日：2012-04-05

申请号：US13012879

申请日：2011-01-25

申请人： Takashi Ando ,  Leslie Charns ,  Jason E. Cummings ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

发明人： Takashi Ando ,  Leslie Charns ,  Jason E. Cummings ,  Lukasz J. Hupka ,  Dinesh R. Koli ,  Tomohisa Konno ,  Mahadevaiyer Krishnan ,  Michael F. Lofaro ,  Jakub W. Nalaskowski ,  Masahiro Noda ,  Dinesh K. Penigalapati ,  Tatsuya Yamanaka

IPC分类号： H01L21/463

CPC分类号： H01L21/31053 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545

摘要： Methods for polishing multiple dielectric layers to form replacement metal gate structures include a first chemical mechanical polish step to remove overburden and planarize a top layer to leave a planarized thickness over a gate structure. A second chemical mechanical polish step includes removal of the thickness to expose an underlying covered surface of a dielectric of the gate structure with a slurry configured to polish the top layer and the underlying covered surface substantially equally to accomplish a planar topography. A third chemical mechanical polish step is employed to remove the dielectric of the gate structure and expose a gate conductor.

摘要翻译： 用于抛光多个电介质层以形成替换金属栅极结构的方法包括第一化学机械抛光步骤，以去除覆盖层并平坦化顶层以在栅极结构上留下平坦化的厚度。 第二化学机械抛光步骤包括去除厚度以暴露栅极结构的电介质的下面覆盖的表面，其中浆料被配置成基本上等同地抛光顶层和下面的被覆表面以实现平面形貌。 采用第三种化学机械抛光步骤来去除栅极结构的电介质并露出栅极导体。

公开(公告)号：US20120074615A1

公开(公告)日：2012-03-29

申请号：US13312189

申请日：2011-12-06

申请人： Takashi Ando ,  Susumu Komoriya ,  Masahiko Ogino ,  Akihiro Miyauchi

发明人： Takashi Ando ,  Susumu Komoriya ,  Masahiko Ogino ,  Akihiro Miyauchi

IPC分类号： B29C59/02

CPC分类号： B29C43/021 ,  B29C43/003 ,  B29C43/58 ,  B29C2043/025 ,  B29C2043/3634 ,  B29C2043/5808 ,  B29L2011/0016 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0002

摘要： There is provided an imprint device for transferring a fine pattern to a material to form a patterned material. The device comprises a stamper having the fine pattern thereon, and a pressure distribution mechanism. The stamper is pressed against the material, and the pressure distribution mechanism provides a nonuniform pressure distribution in a patterned region of the patterned material, while the stamper is in contact with the material. There are provided an imprint device and a microstructure transfer method, by which it is possible to sufficiently spread a resin or other material for forming a pattern layer between a stamper and a patterned material with a lower pressure so as not to damage the stamper or the patterned material, and to form a pattern formation layer having the uniform thickness on the patterned material.

摘要翻译： 提供了用于将精细图案转印到材料以形成图案化材料的压印装置。 该装置包括其上具有精细图案的压模和压力分布机构。 压模被压在材料上，并且压力分配机构在图案化材料的图案化区域中提供不均匀的压力分布，同时压模与材料接触。 提供了压印装置和微结构转印方法，通过该方法可以在压模和图案化材料之间以较低的压力充分地铺展树脂或其它材料以形成图案层，以便不损坏压模或 并且在图案化材料上形成具有均匀厚度的图案形成层。

公开(公告)号：US20110309455A1

公开(公告)日：2011-12-22

申请号：US12816605

申请日：2010-06-16

申请人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

发明人： Takashi Ando ,  Kisik Choi ,  Vijay Narayanan ,  Tenko Yamashita ,  Junli Wang

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/517 ,  H01L21/28079 ,  H01L21/28088 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545

摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.

摘要翻译： 通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。 通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

公开(公告)号：US20110101076A1

公开(公告)日：2011-05-05

申请号：US12907406

申请日：2010-10-19

申请人： Shogo OGAKI ,  Takashi Ando ,  Masaru Inoue

发明人： Shogo OGAKI ,  Takashi Ando ,  Masaru Inoue

IPC分类号： B23K31/02

CPC分类号： B23K3/04 ,  B23K1/0016 ,  G11B5/4833

摘要： A reflow bonding method easily bonds first and second wiring members together by reflowing solder arranged on at least one of first and second bonding parts that are defined on the first and second wiring members, respectively. The method includes positioning the first and second wiring members so that the first and second bonding parts face each other with the solder interposed between them and heating and pressing one of the first and second bonding parts from behind with a pressing face of a heater chip so that the first and second bonding parts lie one on another and so that the solder is heated and reflows to bond the first and second wiring members together

摘要翻译： 回流焊接方法通过分别在第一和第二布线构件上限定的第一和第二接合部中的至少一个上的回流焊料容易地将第一和第二布线构件接合在一起。 该方法包括：定位第一和第二布线构件，使得第一和第二接合部分彼此面对，并且夹在它们之间的焊料并且用加热器片的按压面从后面加热和加压第一和第二接合部分中的一个，从而 第一和第二接合部分彼此位于一起并且使得焊料被加热并且回流以将第一和第二配线构件结合在一起

公开(公告)号：US07928489B2

公开(公告)日：2011-04-19

申请号：US12314804

申请日：2008-12-17

申请人： Takashi Ando

发明人： Takashi Ando

IPC分类号： H01L21/02

CPC分类号： H01L27/11507 ,  H01L27/11502 ,  H01L28/55

摘要： There is formed a gate electrode (word line) via a gate insulating film on a semiconductor substrate, the gate electrode extending in the direction inclining at an angle of approximately 45 degrees to the extending direction of an element region. The element region is divided into three portions by the two gate electrodes. In each element region portion, two MOS transistors are provided. A bit line is connected to a W plug provided in the central region portion and lower electrodes of two ferroelectric capacitors are connected to other W plugs provided in both end region portions. The extending direction of the bit line inclines approximately 45 degrees to the extending direction of the element region.

摘要翻译： 通过半导体衬底上的栅极绝缘膜形成栅电极（字线），栅电极沿与元件区域的延伸方向大致45度的角度倾斜的方向延伸。 元件区域被两个栅电极分成三部分。 在每个元件区域部分中，提供两个MOS晶体管。 位线连接到设置在中央区域部分的W插头，两个铁电电容器的下电极连接到设置在两个端部区域中的其他W插头。 位线的延伸方向相对于元件区域的延伸方向倾斜约45度。

公开(公告)号：US20110058062A1

公开(公告)日：2011-03-10

申请号：US12945217

申请日：2010-11-12

申请人： Yasushi Maruyama ,  Tetsuji Yamaguchi ,  Takashi Ando ,  Susumu Hiyama ,  Yuko Ohgishi

发明人： Yasushi Maruyama ,  Tetsuji Yamaguchi ,  Takashi Ando ,  Susumu Hiyama ,  Yuko Ohgishi

IPC分类号： H04N5/228 ,  H01L31/14

CPC分类号： H01L27/14609 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14685 ,  H01L31/022466 ,  H01L31/022475

摘要： A solid-state imaging device includes a substrate having a first surface and a second surface, light being incident on the second surface side; a wiring layer disposed on the first surface side; a photodetector formed in the substrate and including a first region of a first conductivity type; a transfer gate disposed on the first surface of the substrate and adjacent to the photodetector, the transfer gate transferring a signal charge accumulated in the photodetector; and at least one control gate disposed on the first surface of the substrate and superposed on the photodetector, the control gate controlling the potential of the photodetector in the vicinity of the first surface.

摘要翻译： 固态成像装置包括具有第一表面和第二表面的基板，入射到第二表面侧的光; 布置在所述第一表面侧上的布线层; 形成在所述基板中并且包括第一导电类型的第一区域的光电检测器; 设置在所述基板的所述第一表面上且与所述光电检测器相邻的传输栅极，所述传输栅极传送累积在所述光电检测器中的信号电荷; 以及至少一个控制栅极，其设置在所述基板的所述第一表面上并且重叠在所述光电检测器上，所述控制栅极控制所述光电检测器在所述第一表面附近的电位。

公开(公告)号：US20100193669A1

公开(公告)日：2010-08-05

申请号：US12598691

申请日：2007-08-20

申请人： Tetsuji Yamaguchi ,  Yuko Ohgishi ,  Takashi Ando ,  Harumi Ikeda

发明人： Tetsuji Yamaguchi ,  Yuko Ohgishi ,  Takashi Ando ,  Harumi Ikeda

IPC分类号： H01L27/146 ,  H01L31/18

CPC分类号： H01L27/14636 ,  H01L27/1461 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14645 ,  H01L27/14683 ,  H01L27/14818 ,  H01L27/14868

摘要： Realization of an adequate hole accumulation layer and reduction in dark current are allowed to become mutually compatible. A solid-state imaging device 1 having a light-receiving portion 12 to photoelectrically convert incident light is characterized by including a film 21, which is disposed on a light-receiving surface 12s of the above-described light-receiving portion 12 and which lowers an interface state, and a film 22, which is disposed on the above-described film 21 to lower the interface state and which has a negative fixed charge, wherein a hole accumulation layer 23 is disposed on the light-receiving surface 12s side of the light-receiving portion 12.

摘要翻译： 实现适当的空穴积聚层和减少暗电流被允许变得相互兼容。 具有光电转换入射光的受光部12的固态成像装置1的特征在于，包括设置在上述受光部12的受光面12s上的膜21， 界面状态和膜22，其设置在上述膜21上以降低界面状态并具有负的固定电荷，其中，空穴积累层23设置在该光接收表面12s侧 光接收部分12。

公开(公告)号：US07655457B2

公开(公告)日：2010-02-02

申请号：US10989910

申请日：2004-11-17

申请人： Kosuke Kuwabara ,  Akihiro Miyauchi ,  Masahiko Ogino ,  Takashi Ando

发明人： Kosuke Kuwabara ,  Akihiro Miyauchi ,  Masahiko Ogino ,  Takashi Ando

IPC分类号： C12M1/14 ,  C12M3/04 ,  C12M3/00 ,  C12M1/00

CPC分类号： C12M23/20 ,  C12M21/08 ,  C12M23/10

摘要： It is an object of this invention to provide a cell culture vessel which has a simple and convenient structure, can prevent the injury on the cells at the time of peeling, and accelerates the transportation of nutrients and discharge of waste materials. In order to solve the problem mentioned above, the cell culture vessel of this invention has protrusions having a corresponding diameter not smaller than 10 nm and not greater than 10 μm and a height not smaller than 10 nm and not greater than 1 mm on the surface of the cell culture vessel. The protrusions make the culture fluid permeate into the under part of the cells, accelerate the supply of nutrients and discharge of waste materials, and makes the contact between the cells and the vessel as a point-contact and thereby prevents the cells from the injury which the cells undergo at the time of peeling.

摘要翻译： 本发明的目的是提供一种结构简单方便的细胞培养容器，可以防止剥离时对细胞的损伤，加速营养物质的运输和废料排出。 为了解决上述问题，本发明的细胞培养容器具有相对应的直径不小于10nm且不大于10um的突起，并且在表面上具有不小于10nm且不大于1mm的高度 的细胞培养容器。 突起使得培养液渗透到细胞的下部，加速营养物质的供给和排出废物，并使细胞与血管之间的接触作为点接触，从而防止细胞受损， 细胞在剥离时经历。