公开(公告)号：US5972748A

公开(公告)日：1999-10-26

申请号：US969963

申请日：1997-11-25

申请人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

发明人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

IPC分类号： H01L27/10 ,  H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10808

摘要： A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

摘要翻译： 具有第二接触孔的第一层间绝缘膜形成在外围电路中的半导体衬底1的主表面上。 在第二接触孔中形成有与存储单元阵列中的第一插头电极相同材料的第二插头电极。 在第二插头电极和第一层间绝缘膜的顶表面上形成衬垫层。 焊盘层和电容器下电极由相同的材料制成。 衬垫层被第二层间绝缘膜覆盖。 在位于焊盘层上方的第二层间绝缘膜的一部分处形成第三接触孔。 在第三接触孔中形成第一铝互连层。 因此，可以在DRAM的外围电路中的互连层和半导体衬底的主表面之间容易地形成接触，并且可以简化制造工艺。

公开(公告)号：US5672533A

公开(公告)日：1997-09-30

申请号：US555414

申请日：1995-11-09

申请人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L21/8242 ,  H01L29/68 ,  H01L29/76 ,  H01L29/78 ,  H01L29/92 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L27/1085 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/66659

摘要： Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.

摘要翻译： 公开了一种半导体存储器件，其中可以有效地减少电容器和源极/漏极区域之间的结区中的晶体缺陷和晶体管的短沟道效应。 半导体存储器件包括在电容器连接的栅电极侧，形成为具有比位线侧的侧壁宽度大的侧壁以及源极/漏极区， 电容器被连接并且被形成为具有比相对的源极/漏极区的扩散深度更大的扩散深度。 因此，源极/漏极区域有效地防止在电容器和连接到电容器的源极/漏极区域之间的结区域中产生晶体缺陷，并且侧壁有效地降低了短沟道效应。

公开(公告)号：US5534458A

公开(公告)日：1996-07-09

申请号：US442925

申请日：1995-05-17

申请人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Takeharu Kuroiwa ,  Nobuo Fujiwara ,  Keiichiro Kashihara

IPC分类号： H01L21/28 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/522 ,  H01L27/04 ,  H01L27/105 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L21/3205 ,  H01L28/40 ,  H01L28/55 ,  Y10S257/915 ,  Y10S438/978

摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.

摘要翻译： 根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从 层间绝缘膜的顶面角到掩埋导电层的表面。 因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。

公开(公告)号：US5459345A

公开(公告)日：1995-10-17

申请号：US264092

申请日：1994-06-22

申请人： Tomonori Okudaira ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Keiichiro Kashihara

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/00

CPC分类号： H01L27/10852

摘要： An object of the invention is to provide a semiconductor device which has a capacitor having good anti-leak characteristics and good breakdown voltage characteristics and is suitable to high integration. Source/drain regions (25) are formed at a surface of a silicon substrate (31). Interlayer insulating films (1) and (3) having contact holes (1a) and (3a), through which a surfaces of the source/drain region is partially exposed, is formed on the surface of silicon substrate (31). Contact holes (1a) and (3a) are filled with plug layer (9a). A capacitor (20) having a highly dielectric film (15) is formed such that it is electrically connected to source/drain region (25) through plug layer (9a). The interlayer insulating film is formed of a two-layer structure including a silicon oxide film (1) and a silicon nitride film (3). Silicon nitride film (3) and plug layer (9a) have the top surfaces flush with each other.

摘要翻译： 本发明的目的是提供一种半导体器件，其具有具有良好的防漏电特性和良好的击穿电压特性的电容器，并且适用于高集成度。 源极/漏极区（25）形成在硅衬底（31）的表面。 在硅衬底（31）的表面上形成具有接触孔（1a）和（3a）的层间绝缘膜（1）和（3），源极/漏极区域的表面部分露出。 接触孔（1a）和（3a）填充有塞层（9a）。 具有高电介质膜（15）的电容器（20）形成为通过插塞层（9a）与源极/漏极区域（25）电连接。 层间绝缘膜由包括氧化硅膜（1）和氮化硅膜（3）的两层结构形成。 氮化硅膜（3）和插塞层（9a）的上表面彼此齐平。

公开(公告)号：US5164806A

公开(公告)日：1992-11-17

申请号：US698690

申请日：1991-05-13

申请人： Masao Nagatomo ,  Hiroki Shimano ,  Tomonori Okudaira ,  Yoshinori Okumura

发明人： Masao Nagatomo ,  Hiroki Shimano ,  Tomonori Okudaira ,  Yoshinori Okumura

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L21/765

CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/76216 ,  H01L21/765 ,  H01L29/6656 ,  Y10S257/90

摘要： An element isolating structure employed for isolating the elements of a semiconductor substrate has an impurity region having a concentration lower than that of a source/drain and a channel stop region, between the source/drain of an MOS transistor formed in an active region, and the channel stop region formed under an LOCOS film.A field shield isolating structure has a low concentrated impurity region between the source/drain of an MOS transistor formed in the active region and the substrate surface region covered by a field shield electrode layer. The low concentrated impurity region improves its junction breakdown voltage in the boundary region with the element isolating region.An improved LOCOS film is formed into an amorphous region on the surface of the substrate by an oblique rotating ion implanting method, and the amorphous region is formed by thermal oxidation. The method suppresses the emergence of a bird's beak.

摘要翻译： 用于隔离半导体衬底的元件的元件隔离结构具有在有源区中形成的MOS晶体管的源极/漏极之间具有低于源极/漏极和沟道截止区域的浓度的杂质区域和 在LOCOS膜下形成的通道停止区域。 场屏蔽隔离结构在有源区中形成的MOS晶体管的源极/漏极与由场屏蔽电极层覆盖的衬底表面区域之间具有低浓度杂质区域。 低浓度杂质区域改善了与元件隔离区域的边界区域的结击穿电压。 通过倾斜旋转离子注入方法将改进的LOCOS膜形成在衬底的表面上的非晶区域中，通过热氧化形成非晶区域。 该方法抑制鸟喙的出现。

公开(公告)号：US08338247B2

公开(公告)日：2012-12-25

申请号：US12720174

申请日：2010-03-09

申请人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

发明人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.

摘要翻译： 提高半导体器件的性能。 在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中 形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。 之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后 在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。 金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

公开(公告)号：US08022445B2

公开(公告)日：2011-09-20

申请号：US12510026

申请日：2009-07-27

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：制备具有平面方向为表面（100）的主表面的硅衬底; 形成具有栅电极，源极区，漏极区和沟道长度方向平行于硅衬底的晶体取向<100°的沟道的n沟道MISFET（金属绝缘体半导体场效应晶体管）; 并且在相同的步骤上在源极区域和漏极区域上在栅电极和NiSi 2上形成NiSi。

公开(公告)号：US07936016B2

公开(公告)日：2011-05-03

申请号：US12413980

申请日：2009-03-30

申请人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

发明人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

IPC分类号： H01L29/76

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

公开(公告)号：US20100230761A1

公开(公告)日：2010-09-16

申请号：US12720174

申请日：2010-03-09

申请人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

发明人： Tadashi Yamaguchi ,  Toshiaki Tsutsumi ,  Satoshi Ogino ,  Kazumasa Yonekura ,  Kenji Kawai ,  Yoshihiro Miyagawa ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Kotaro Kihara

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： To improve the performance of semiconductor devices. Over an n+-type semiconductor region for source/drain of an n-channel type MISFET and a first gate electrode, and over a p+-type semiconductor region for source/drain of a p-channel type MISFET and a second gate electrode, which are formed over a semiconductor substrate, a metal silicide layer including nickel platinum silicide is formed by a salicide process. After that, a tensile stress film is formed over the whole face of the semiconductor substrate, and then the tensile stress film over the p-channel type MISFET is removed by dry-etching, and, after a compression stress film is formed over the whole face of the semiconductor substrate, the compression stress film over the n-channel type MISFET is removed by dry-etching. The Pt concentration in the metal silicide layer is highest at the surface, and becomes lower as the depth from the surface increases.

摘要翻译： 提高半导体器件的性能。 在用于n沟道型MISFET和第一栅电极的源极/漏极的n +型半导体区域上，以及用于p沟道型MISFET和第二栅电极的源极/漏极的p +型半导体区域上，其中 形成在半导体衬底上，通过自对准硅化物工艺形成包括镍铂硅化物的金属硅化物层。 之后，在半导体基板的整个面上形成拉伸应力膜，然后通过干法蚀刻去除p沟道型MISFET上的拉伸应力膜，并且在整个压电应力膜形成之后 在半导体衬底的表面上，通过干蚀刻去除n沟道型MISFET上的压缩应力膜。 金属硅化物层中的Pt浓度在表面处最高，并且随着从表面的深度增加而变低。

公开(公告)号：US20090079007A1

公开(公告)日：2009-03-26

申请号：US12211925

申请日：2008-09-17

申请人： TADASHI YAMAGUCHI ,  Keiichiro Kashihara ,  Toshiaki Tsutsumi ,  Tomonori Okudaira

发明人： TADASHI YAMAGUCHI ,  Keiichiro Kashihara ,  Toshiaki Tsutsumi ,  Tomonori Okudaira

IPC分类号： H01L29/00 ,  H01L21/8238

CPC分类号： H01L29/045 ,  H01L21/823807 ,  H01L27/105 ,  H01L27/11 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： The present invention can prevent occurrence of an off-leak current in the NMISFETs formed over the Si (110) substrate and having a silicided source/drain region. The semiconductor device includes N channel MISFETs (Metal Insulator Semiconductor Field Effect Transistors) which are formed over a semiconductor substrate having a main surface with a (110) plane orientation and have a source region and a drain region at least one of which has thereover nickel silicide or a nickel alloy silicide. Of these NMISFETs, those having a channel width less than 400 nm are laid out so that their channel length direction is parallel to a crystal orientation.

摘要翻译： 本发明可以防止在Si（110）衬底上形成的具有硅化源极/漏极区域的NMISFET中产生漏电流。 半导体器件包括N沟道MISFET（金属绝缘体半导体场效应晶体管），其形成在具有（110）面取向的主表面的半导体衬底上，并且具有源极区和漏极区，其中至少一个具有镍 硅化物或镍合金硅化物。 在这些NMISFET中，沟道宽度小于400nm的那些被布置成使得它们的沟道长度方向平行于<100>晶体取向。