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    Write Protection for a non-volatile memory
    32.
    发明授权
    Write Protection for a non-volatile memory 有权
    写保护用于非易失性存储器

    公开(公告)号：US5912849A

    公开(公告)日：1999-06-15

    申请号：US141564

    申请日：1998-08-28

    申请人： Yoshihiko Yasu ,  Hiroyuki Sakai ,  Michael W. Yeager ,  Donald J. Verhaeghe

    发明人： Yoshihiko Yasu ,  Hiroyuki Sakai ,  Michael W. Yeager ,  Donald J. Verhaeghe

    IPC分类号： G11C16/02 ,  G06F12/14 ,  G06F21/02 ,  G11C7/24 ,  G11C11/22 ,  G11C7/00

    CPC分类号： G11C7/24 ,  G11C11/22

    摘要： A semiconductor memory device, divided into plural blocks, comprising: a memory array having a non-volatile memory element which makes the read cycle and the write cycle to be substantially equivalent; plural storage elements storing the information of write protection/permission corresponding to each said block respectively; and a setting circuit to set the information of write protection/permission to said plural storage elements, wherein said setting circuit sets the write-protection information to said plural storage elements at the write cycle after designated plural read cycles. Therefore, the write protection/permission can be set by the unit of block, block by block, so that the write-protected ROM and the RAM can be set freely. Furthermore, the complexity of the setting procedure of write protection/permission may prevent the accidental false setting caused by a system runaway and so forth.

    摘要翻译： 一种分割成多个块的半导体存储器件，包括：具有非易失性存储元件的存储器阵列，其使读周期和写周期基本上相等; 多个存储元件分别存储与每个所述块相对应的写保护/许可信息; 以及设置电路，用于将所述多个存储元件的写入保护/许可信息设置，其中所述设置电路在指定的多个读取周期之后以写入周期将写入保护信息设置为所述多个存储元件。 因此，写保护/许可可以通过块单位来逐块设置，从而可以自由设置写保护ROM和RAM。 此外，写保护/许可的设置过程的复杂性可以防止由系统失控引起的意外错误设置等。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    35.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20080224177A1

    公开(公告)日：2008-09-18

    申请号：US12126019

    申请日：2008-05-23

    申请人： Satoshi Umekita ,  Tomomi Ajioka ,  Kenji Hirose ,  Yoshihiko Yasu ,  Yujiro Miyairi

    发明人： Satoshi Umekita ,  Tomomi Ajioka ,  Kenji Hirose ,  Yoshihiko Yasu ,  Yujiro Miyairi

    IPC分类号： H01L27/10

    CPC分类号： H01L27/0203

    摘要： Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on the left side of the core power source regions 4 to 8 and at the upper and lower parts of the semiconductor integrated circuit device 1. A power switch region for repeater 11 is formed so as to surround the core power source regions 2 to 8 and the repeater regions 10. The power source lines of the reference potential connected to the repeater regions 10 are laid out at equally spaced intervals throughout the core power source regions 2 to 8, which enables the repeater regions 10 to be flexibly laid out. This permits the repeaters to be more effectively arranged, which improves the performances of semiconductor integrated circuit device 1.

    摘要翻译： 中继器被布置在任意位置以显着提高信号的传输速度。 在半导体集成电路装置1中，在核心电源区域2,3和5的核心电源区域4的左侧设置有作为布线用继电器点的中继器的中继器区域10， 并且在半导体集成电路装置1的上部和下部。 中继器11的电源开关区域形成为围绕核心电源区域2至8和中继器区域10。 连接到中继器区域10的参考电位的电源线在整个核心电源区域2至8中以均匀间隔布置，这使得中继器区域10能够被灵活布置。 这允许更有效地布置中继器，这改善了半导体集成电路装置1的性能。

    Semiconductor integrated circuit device
    36.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07394143B2

    公开(公告)日：2008-07-01

    申请号：US11652013

    申请日：2007-01-11

    申请人： Satoshi Umekita ,  Tomomi Ajioka ,  Kenji Hirose ,  Yoshihiko Yasu ,  Yujiro Miyairi

    发明人： Satoshi Umekita ,  Tomomi Ajioka ,  Kenji Hirose ,  Yoshihiko Yasu ,  Yujiro Miyairi

    IPC分类号： H01L29/00

    CPC分类号： H01L27/0203

    摘要： Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on the left side of the core power source regions 4 to 8 and at the upper and lower parts of the semiconductor integrated circuit device 1. A power switch region for repeater 11 is formed so as to surround the core power source regions 2 to 8 and the repeater regions 10. The power source lines of the reference potential connected to the repeater regions 10 are laid out at equally spaced intervals throughout the core power source regions 2 to 8, which enables the repeater regions 10 to be flexibly laid out. This permits the repeaters to be more effectively arranged, which improves the performances of semiconductor integrated circuit device 1.

    摘要翻译： 中继器被布置在任意位置以显着提高信号的传输速度。 在半导体集成电路装置1中，在核心电源区域2,3和5的核心电源区域4的左侧设置有作为布线用继电器点的中继器的中继器区域10， 并且在半导体集成电路装置1的上部和下部。 中继器11的电源开关区域形成为围绕核心电源区域2至8和中继器区域10。 连接到中继器区域10的参考电位的电源线在整个核心电源区域2至8中以均匀间隔布置，这使得中继器区域10能够被灵活布置。 这允许更有效地布置中继器，这改善了半导体集成电路装置1的性能。

    Semiconductor integrated circuit device
    37.
    发明申请
    Semiconductor integrated circuit device 审中-公开
    半导体集成电路器件

    公开(公告)号：US20050232053A1

    公开(公告)日：2005-10-20

    申请号：US11109660

    申请日：2005-04-20

    申请人： Yuri Azuma ,  Yoshihiko Yasu ,  Yasuto Igarashi ,  Takashi Kuraishi ,  Kazumasa Yanagisawa

    发明人： Yuri Azuma ,  Yoshihiko Yasu ,  Yasuto Igarashi ,  Takashi Kuraishi ,  Kazumasa Yanagisawa

    IPC分类号： H01L21/822 ,  G11C5/00 ,  G11C5/14 ,  H01L27/04 ,  H03K19/00 ,  H03K19/0175

    CPC分类号： G11C5/147

    摘要： A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has a first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed, wherein the second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with the control signal which was responded to when the second power supply state was instructed by the third circuit block to the first circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block.

    摘要翻译： 提供一种在实现多功能化和省电的同时提高设计效率的半导体集成电路装置。 半导体集成电路器件具有第一至第三电路块，并且被置于第一电源状态，其中根据来自第三电路块的指令或第二电源确保第一电路块中的内部电路的操作 其中第二电路块具有接收从第一电路块提供的信号的输入单元，并且第二电路块的输入单元具有根据本发明的输入电路，其中内部电路的操作不被保证， 当第三电路块向第一电路块指示第二电源状态时响应的控制信号使得将特定信号电平维持为与第二电路块的工作电压无关，而与信号无关 由第一电路块提供。

    Semiconductor integrated circuit device
    40.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08063691B2

    公开(公告)日：2011-11-22

    申请号：US13020169

    申请日：2011-02-03

    申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yoshihiko Yasu ,  Nobuhiro Oodaira

    发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yoshihiko Yasu ,  Nobuhiro Oodaira

    IPC分类号： H03L5/00

    CPC分类号： H03K19/0016 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

    摘要翻译： 具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO1的半导体集成电路器件。 第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。 转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。 转换电路（MIO1〜MIO4）通常用于连接电路块。