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    SEMICONDUCTOR CHIP
    3.
    发明申请
    SEMICONDUCTOR CHIP 有权
    半导体芯片

    公开(公告)号：US20120049899A1

    公开(公告)日：2012-03-01

    申请号：US13184030

    申请日：2011-07-15

    申请人： Hiromi Notani ,  Issei Kashima

    发明人： Hiromi Notani ,  Issei Kashima

    IPC分类号： G05F3/02

    CPC分类号： G05F1/56 ,  G05F1/575 ,  G05F3/242

    摘要： The present invention provides a semiconductor chip which is insusceptible to noise and whose consumption current is small. In a semiconductor chip, an internal power supply voltage for an internal circuit block is generated by a regulator having small current drive capability and a regulator having large current drive capability. A voltage buffer is provided between a reference voltage generating circuit and the regulator having large current drive capability. In a low-speed operation mode, the voltage buffer and the regulator having large current drive capability are made inactive. Therefore, noise in reference voltage is suppressed, and consumption current can be reduced.

    摘要翻译： 本发明提供一种对噪声不敏感且消耗电流小的半导体芯片。 在半导体芯片中，用于内部电路块的内部电源电压由具有小电流驱动能力的调节器和具有大电流驱动能力的调节器产生。 在参考电压发生电路和具有大电流驱动能力的调节器之间提供电压缓冲器。 在低速运行模式中，具有大电流驱动能力的电压缓冲器和调节器变为无效。 因此，能够抑制基准电压的噪声，能够降低消耗电流。

    Semiconductor integrated circuit device including a level shifter
    4.
    发明授权
    Semiconductor integrated circuit device including a level shifter 失效
    包括电平转换器的半导体集成电路器件

    公开(公告)号：US06998668B2

    公开(公告)日：2006-02-14

    申请号：US10246654

    申请日：2002-09-19

    申请人： Yasunobu Nakase ,  Hiromi Notani

    发明人： Yasunobu Nakase ,  Hiromi Notani

    IPC分类号： H01L29/94

    CPC分类号： H01L27/0222 ,  H01L27/0805 ,  H03K3/356008 ,  H03K3/356113 ,  H03K17/063 ,  H03K17/102 ,  H03K17/223 ,  H03K19/00315 ,  H03K19/018521

    摘要： A semiconductor integrated circuit device is provided, in which a node from which an output signal of a level shifter is sent can be initialized such that the potential thereof be set at a desired logic level at the time of power supply.The semiconductor integrated circuit device includes a level shifter 6 and two capacitors N10 and C0. The level shifter 6 receives an input signal and converts the received signal to a signal having a voltage amplitude greater than that of the received signal, then to provide the signal to a node D3. The capacitor N10 is connected to the node D3, and the capacitor C0 is connected in series with the capacitor N10. The capacitor N10 is formed of a MOS transistor having a gate connected to the node D3 and a source and a drain both connected to the capacitor C0.

    摘要翻译： 提供了一种半导体集成电路器件，其中从其发送电平移位器的输出信号的节点可以被初始化，使得其电位在供电时被设置为期望的逻辑电平。

    High impedance detecting circuit and interface circuit
    5.
    发明授权
    High impedance detecting circuit and interface circuit 失效
    高阻抗检测电路和接口电路

    公开(公告)号：US5874835A

    公开(公告)日：1999-02-23

    申请号：US719888

    申请日：1996-09-25

    申请人： Masahiko Ishiwaki ,  Harufusa Kondoh ,  Hiromi Notani

    发明人： Masahiko Ishiwaki ,  Harufusa Kondoh ,  Hiromi Notani

    IPC分类号： G01R31/317 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/00 ,  H03K19/02

    CPC分类号： H03K19/003

    摘要： A voltage applying means applies a voltage which determines the logical value of a node to the node, with the signal at the node fixed. Then, an applied voltage removing means removes the voltage applied by the voltage applying means. First and second detecting means detects the logical value of the node before and after the voltage application and removal of the applied voltage. A judging means compares the results of detection of the first and second detecting means to judge whether or not the node is at a high impedance.

    摘要翻译： 电压施加装置将确定节点的逻辑值的电压施加到节点，同时节点处的信号被固定。 然后，施加的电压去除装置去除由电压施加装置施加的电压。 第一和第二检测装置检测在施加电压和施加的电压的去除之前和之后节点的逻辑值。 判断装置比较第一和第二检测装置的检测结果，以判断节点是否处于高阻抗。

    Output circuit and interface system comprising the same
    6.
    发明授权
    Output circuit and interface system comprising the same 失效
    输出电路和包含它的接口系统

    公开(公告)号：US5235222A

    公开(公告)日：1993-08-10

    申请号：US813627

    申请日：1991-12-26

    申请人： Harufusa Kondoh ,  Hiromi Notani

    发明人： Harufusa Kondoh ,  Hiromi Notani

    IPC分类号： H04L25/02 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0185 ,  H04Q3/42

    CPC分类号： H03K19/00361 ,  H03K19/018557

    摘要： An output circuit 1 comprises a constant current source 11, a switch 12, and an output pad 14. The switch 12 is connected between the constant current source 11 and the output pad 14. A transmission path 3 is connected to the output pad 14. The transmission path 3 is coupled to a terminator voltage V.sub.TT by a resistor for pull up. Reflection of a signal or generation of noise can be suppressed by bringing the resistance value of the resistor 4 close to a characteristic impedance of the transmission path 3. A voltage amplitude on the transmission path 3 can be determined arbitrarily by adjusting current value of the constant current source 11 and resistance value of the resistor 4.

    摘要翻译： 输出电路1包括恒流源11，开关12和输出垫14.开关12连接在恒流源11和输出垫14之间。传输路径3连接到输出焊盘14。 传输路径3通过用于上拉的电阻器耦合到终端电压VTT。 可以通过使电阻器4的电阻值接近传输路径3的特性阻抗来抑制信号的反射或产生噪声。传输路径3上的电压振幅可以通过调整常数的电流值来任意确定 电流源11和电阻器4的电阻值。

    Data storage circuit
    7.
    发明授权
    Data storage circuit 失效
    数据存储电路

    公开(公告)号：US07345936B2

    公开(公告)日：2008-03-18

    申请号：US10739090

    申请日：2003-12-19

    申请人： Hiromi Notani

    发明人： Hiromi Notani

    IPC分类号： G11C7/00

    CPC分类号： G11C11/412

    摘要： A data storage circuit having a plurality of memory cells (S1), a plurality of bit lines (BL, /BL) and a precharge circuit further comprises a discharge circuit. In an operating mode of the data storage circuit, the bit lines (BL, /BL) are precharged by the precharge circuit under the control on the basis of a chip enable signal (CE) before write or read of data into/from the memory cells (S1) and in a standby state, the bit lines (BL, /BL) are discharged by the discharge circuit. Further, also in a sleep mode, the bit lines (BL, /BL) are discharged by the discharge circuit. With this circuit configuration and operation, it is possible to provide the data storage circuit which allows reduction in standby power consumption by suppressing standby currents in the standby state.

    摘要翻译： 具有多个存储单元（S1），多个位线（BL，/ BL）和预充电电路的数据存储电路还包括放电电路。 在数据存储电路的操作模式中，在将数据写入或读出存储器之前，在基于芯片使能信号（CE）的控制下，位线（BL，/ BL）由预充电电路预充电 单元（S1）并且在待机状态下，位线（BL，/ BL）由放电电路放电。 此外，在睡眠模式中，位线（BL，/ BL）也被放电电路放电。 利用该电路配置和操作，可以提供通过抑制待机状态下的待机电流来允许降低待机功耗的数据存储电路。

    Delay locked loop circuit
    8.
    发明授权
    Delay locked loop circuit 失效
    延时锁定回路电路

    公开(公告)号：US5994934A

    公开(公告)日：1999-11-30

    申请号：US111875

    申请日：1998-07-08

    申请人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe ,  Harufusa Kondoh ,  Hiromi Notani

    发明人： Tsutomu Yoshimura ,  Yasunobu Nakase ,  Yoshikazu Morooka ,  Naoya Watanabe ,  Harufusa Kondoh ,  Hiromi Notani

    IPC分类号： G06F1/10 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03K5/131 ,  H03L7/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/095 ,  H03L7/06

    CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/095

    摘要： Provided is a DLL circuit that can execute a precise delay synchronization operation without increasing the variable delay time range of a delay line. The DLL circuit comprises a phase comparator (3), a charge pump (6), an LPF (8) and a delay line (9), and operates to match phases of an input signal (CLKIN) and a feedback signal (FBCLK). The phase comparator (3) always outputs a phase comparison result that causes a delay time of the delay line (9) to increase, at the time of initial operation after a reset operation. The LPF (8) outputs a delay adjusting signal (S8) indicating that a delay time due to the delay line (9) becomes the minimum, in executing a reset.

    摘要翻译： 提供了可以在不增加延迟线的可变延迟时间范围的情况下执行精确的延迟同步操作的DLL电路。 DLL电路包括相位比较器（3），电荷泵（6），LPF（8）和延迟线（9），并且操作以匹配输入信号（CLKIN）和反馈信号（FBCLK）的相位， 。 相位比较器（3）总是输出在复位操作之后的初始操作时延迟线（9）的延迟时间增加的相位比较结果。 在执行复位时，LPF（8）输出指示由于延迟线（9）引起的延迟时间变为最小的延迟调整信号（S8）。