公开(公告)号：US20130069235A1

公开(公告)日：2013-03-21

申请号：US13235491

申请日：2011-09-18

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L23/485

CPC分类号： H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05085 ,  H01L2224/05095 ,  H01L2224/05624

摘要： A bonding pad structure includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers comprising at least a topmost IMD layer; a bondable metal pad layer disposed on a surface of the topmost IMD layer within a pad forming region; a passivation layer covering a periphery of the bondable metal pad layer and the surface of the topmost IMD layer; anda plurality of via plugs disposed in the topmost IMD layer within an annular region of the pad forming region, wherein the via plugs are not formed in a central region of the pad forming region.

摘要翻译： 焊盘结构包括其上具有包括至少最上面的IMD层的多个金属间电介质（IMD）层的半导体衬底; 可焊接金属焊盘层，其设置在焊盘形成区域内的最上层IMD层的表面上; 覆盖可焊接金属焊盘层的周边和最上面的IMD层的表面的钝化层; 以及设置在焊盘形成区域的环形区域内的最上层IMD层中的多个通孔，其中通孔塞不形成在焊盘形成区域的中心区域中。

公开(公告)号：US07067418B2

公开(公告)日：2006-06-27

申请号：US10908824

申请日：2005-05-27

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Chih-Ching Lin

IPC分类号： H01L21/4763

CPC分类号： H01L21/7685 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76837

摘要： A method for fabricating interconnects is provided. The method comprises forming a conducting line on a first dielectric layer; forming a first liner layer on the surfaces of the first dielectric layer and the conducting line; forming a second liner layer on the first liner layer; forming a second dielectric layer on the second liner layer, wherein the etching selectivity rate of the second dielectric layer is higher than the etching selectivity rate of the second liner; and patterning the second dielectric layer to form a contact window opening through the second liner layer and the first liner layer to expose the surface of the conducting line. Because the second dielectric layer having an etching rate higher than the etching rate of the second liner layer, the second liner layer can be used as an etch stop layer while patterning the second dielectric layer.

公开(公告)号：US20050148152A1

公开(公告)日：2005-07-07

申请号：US10751503

申请日：2004-01-06

申请人： Hsiu-Chun Lee ,  Tse-Yao Huang ,  Yi-Nan Chen

发明人： Hsiu-Chun Lee ,  Tse-Yao Huang ,  Yi-Nan Chen

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/76 ,  H01L21/311

CPC分类号： H01L21/3081 ,  H01L21/3086 ,  H01L21/76224

摘要： Disclosed is a method for forming a shallow trench. The method of the present invention comprises steps of providing a substrate; forming a plurality of operation layers on the substrate; forming photoresist on the uppermost one of the operation layers to define a position to be etched; etching a portion of the operation layers at said position to form an opening; forming a spacing layer on the sidewall of the opening; and etching a portion of the substrate corresponding to the opening to form a shallow trench. By the etching method of the present invention, a striation phenomenon caused by the common mask etch is avoided.

摘要翻译： 公开了一种形成浅沟槽的方法。 本发明的方法包括提供基底的步骤; 在所述基板上形成多个操作层; 在最上面的操作层上形成光致抗蚀剂以限定待蚀刻的位置; 在所述位置蚀刻操作层的一部分以形成开口; 在所述开口的侧壁上形成间隔层; 并且蚀刻对应于所述开口的所述基板的一部分以形成浅沟槽。 通过本发明的蚀刻方法，避免了由普通掩模蚀刻引起的条纹现象。

公开(公告)号：US20050136674A1

公开(公告)日：2005-06-23

申请号：US10740680

申请日：2003-12-22

申请人： Tse-Yao Huang ,  Yi-Nan Chen

发明人： Tse-Yao Huang ,  Yi-Nan Chen

IPC分类号： H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8242

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L27/10888 ,  H01L27/10894

摘要： Disclosed is an improved method for forming contact holes. The method of the present invention comprises the steps of providing a substrate; forming a plurality of operation layers on the substrate as necessary; forming a poly-silicon layer on the uppermost one of the operation layers; forming an anti-reflective layer on the poly-silicon layer; forming a photoresist layer on the anti-reflective layer to define the positions where the contact holes are to be formed; removing portions of the anti-reflective layer not covered with the photoresist layer; removing the photoresist layer; removing portions of the poly-silicon layer not covered with the anti-reflective layer; and using the residual poly-silicon layer as a mask to etch and form the contact holes. In the step of removing portions of the poly-silicon layer comprises partially removing portions of the poly-silicon not covered with the anti-reflective layer to form recesses, removing the anti-reflective layer, and opening the recesses of the poly-silicon to form openings

摘要翻译： 公开了一种形成接触孔的改进方法。 本发明的方法包括提供基底的步骤; 根据需要在基板上形成多个操作层; 在最上面的一个操作层上形成多晶硅层; 在所述多晶硅层上形成抗反射层; 在抗反射层上形成光致抗蚀剂层以限定要形成接触孔的位置; 去除未被光致抗蚀剂层覆盖的抗反射层的部分; 去除光致抗蚀剂层; 去除未被抗反射层覆盖的多晶硅层的部分; 并使用剩余的多晶硅层作为掩模来蚀刻和形成接触孔。 在去除多晶硅层的部分的步骤中，包括部分地去除未被抗反射层覆盖的多晶硅的部分以形成凹部，去除抗反射层，并将多晶硅的凹部打开至 形成开口

公开(公告)号：US08642479B2

公开(公告)日：2014-02-04

申请号：US13183358

申请日：2011-07-14

申请人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chih-Ching Lin ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/302

CPC分类号： H01L21/76802 ,  H01L21/31144 ,  H01L21/32137

摘要： A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

摘要翻译： 提供了一种在半导体器件中形成开口的方法，包括：向半导体衬底提供其上顺序形成的氧化硅层，多晶硅层和氮化硅层; 图案化氮化硅层，在氮化硅层中形成第一开口，其中第一开口暴露多晶硅层的顶表面; 使用包括溴化氢（HBr），氧（O 2）和碳氟化合物（C x F y）的气体蚀刻剂进行第一蚀刻工艺，在多晶硅层中形成第二开口，其中与第二开口相邻的多晶硅层的侧壁基本上 垂直于氧化硅层的顶表面，其中x在1-5之间，y在2-8之间; 去除氮化硅层; 以及进行第二蚀刻工艺，在由所述第二开口暴露的所述氧化硅层中形成第三开口。

公开(公告)号：US08551881B2

公开(公告)日：2013-10-08

申请号：US13093735

申请日：2011-04-25

申请人： Shing-Yih Shih ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Shing-Yih Shih ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/44

CPC分类号： H01L21/304 ,  H01L21/76898

摘要： A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias.

摘要翻译： 公开了一种斜面修整三维（3D）半导体器件的方法，包括提供衬底上的堆叠层，并通过其中的衬底通孔（TSV），其中衬底的边缘是弯曲的，对弯曲的 边缘，用于获得平面边缘，并且使基板变薄以暴露通过的基板通孔。

公开(公告)号：US08487397B2

公开(公告)日：2013-07-16

申请号：US13093742

申请日：2011-04-25

申请人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L23/52

CPC分类号： H01L23/485 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.

摘要翻译： 具有自对准接触的集成电路包括其上形成有晶体管的衬底，介电间隔物，保护屏障和导电层。 晶体管包括掩模层和形成在掩模层的相对侧上的一对绝缘间隔物。 电介质间隔物部分地覆盖晶体管的至少一个绝缘间隔物。 保护屏障形成在电介质间隔物上。 导电层形成在掩模层，保护屏障，电介质间隔物，绝缘间隔物和介电间隔物上，作为用于接触晶体管的源/漏区的自对准接触。

公开(公告)号：US20130099309A1

公开(公告)日：2013-04-25

申请号：US13281293

申请日：2011-10-25

申请人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jeng-Hsing Jang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/823487 ,  H01L27/0266 ,  H01L29/0692 ,  H01L29/4238 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions.

摘要翻译： 公开了一种垂直MOSFET静电放电装置，包括：包括多个沟槽的衬底;设置在每个沟槽中的凹入栅极，设置在两个相邻凹入栅极中的每一个之间的漏极区域，设置在每个漏极区域下方的静电放电注入区域， 以及围绕并设置在凹入栅极和静电放电注入区域下面的源极区域。

公开(公告)号：US08415729B2

公开(公告)日：2013-04-09

申请号：US13081500

申请日：2011-04-07

申请人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L27/108

CPC分类号： H01L29/7397 ,  H01L29/4236 ,  H01L29/66348

摘要： A power device with trenched gate structure, includes: a substrate having a first face and a second face opposing to the first face, a body region of a first conductivity type disposed in the substrate, a base region of a second conductivity type disposed in the body region, a cathode region of the first conductivity type disposed in the base region, an anode region of the second conductivity type disposed in the substrate at the second face a trench disposed in the substrate and extending from the first face into the body region, and the cathode region encompassing the trench, wherein the trench has a wavelike sidewall, a gate structure disposed in the trench and an accumulation region disposed in the body region and along the wavelike sidewall. The wavelike sidewall can increase the base current of the bipolar transistor and increase the performance of the IGBT.

摘要翻译： 具有沟槽栅极结构的功率器件包括：具有第一面和与第一面相对的第二面的衬底，设置在衬底中的第一导电类型的主体区域，设置在第二导电类型的基极区域 设置在所述基底区域中的所述第一导电类型的阴极区域，所述第二导电类型的阳极区域设置在所述基板的所述第二面处，所述沟槽设置在所述基板中并且从所述第一面延伸到所述主体区域中， 以及包围所述沟槽的阴极区域，其中所述沟槽具有波状侧壁，设置在所述沟槽中的栅极结构以及设置在所述体区中并沿着所述波浪形侧壁的堆积区域。 波浪形侧壁可以增加双极晶体管的基极电流并增加IGBT的性能。

公开(公告)号：US20130078815A1

公开(公告)日：2013-03-28

申请号：US13244013

申请日：2011-09-23

申请人： Chang-Ming Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Chang-Ming Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/3065

CPC分类号： H01L21/31116 ,  B23K10/003 ,  B23K2101/40

摘要： A method for forming a semiconductor structure with reduced line edge roughness is provided, including: providing a device layer with a patterned photoresist layer formed thereon; and performing a plasma etching process to pattern the device layer with the patterned photoresist layer formed thereon, forming a patterned device layer, wherein the plasma etching process is operated under a continuous on-stage voltage provided with a relative higher frequency and an on-off stage voltage with pulsing modulation provided with a relative lower frequency.

摘要翻译： 提供了一种形成具有线边缘粗糙度降低的半导体结构的方法，包括：提供其上形成有图案化光致抗蚀剂层的器件层; 以及执行等离子体蚀刻工艺以对其上形成有图案化的光致抗蚀剂层进行图案化，形成图案化的器件层，其中等离子体蚀刻工艺在具有相对较高频率和开关的连续的阶段电压下操作 脉冲调制的阶段电压具有相对较低的频率。