公开(公告)号：US11706993B2

公开(公告)日：2023-07-18

申请号：US17134460

申请日：2020-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L43/12 ,  H10N50/10 ,  H01L21/768 ,  H01L21/762 ,  H10N50/80 ,  H10N35/01

CPC classification number: H10N50/10 ,  H01L21/762 ,  H01L21/76802 ,  H10N50/80 ,  H10N35/01

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

公开(公告)号：US11581438B2

公开(公告)日：2023-02-14

申请号：US16992061

申请日：2020-08-12

Applicant: United Microelectronics Corp.

Inventor： Hao Che Feng ,  Hung Jen Huang ,  Hsin Min Han ,  Shih-Wei Su ,  Ming Shu Chiu ,  Pi-Hung Chuang ,  Wei-Hao Huang ,  Shao-Wei Wang ,  Ping Wei Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

Abstract: The invention provides a fin structure for a fin field effect transistor, including a substrate. The substrate includes a plurality of silicon fins, wherein a top of each one of the silicon fins is a round-like shape in a cross-section view. An isolation layer is disposed on the substrate between the silicon fins at a lower portion of the silicon fins while an upper portion of the silicon fins is exposed. A stress buffer layer is disposed on a sidewall of the silicon fins between the isolation layer and the lower portion of the silicon fins. The stress buffer layer includes a nitride portion.

公开(公告)号：US20220189770A1

公开(公告)日：2022-06-16

申请号：US17147477

申请日：2021-01-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Hao-Che Feng ,  Hsuan-Tai Hsu ,  Chun-Yu Chen ,  Wei-Hao Huang ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/762

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a fin-shaped structure on a substrate, forming a dielectric layer surrounding the fin-shaped structure, performing an anneal process to transform the dielectric layer into a shallow trench isolation (STI), removing the fin-shaped structure to form a trench, and forming a stack structure in the trench. Preferably, the stack structure includes a first semiconductor layer on the fin-shaped structure and a second semiconductor layer on the first semiconductor layer and the first semiconductor layer and the second semiconductor layer include different materials.

公开(公告)号：US20220085283A1

公开(公告)日：2022-03-17

申请号：US17533003

申请日：2021-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Tai-Cheng Hou ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Chin-Yang Hsieh ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Bin-Siang Tsai ,  Kun-Ju Li ,  Chih-Yueh Li ,  Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Yu-Tsung Lai ,  Wei-Hao Huang

IPC: H01L43/08 ,  H01L21/768 ,  H01L43/02 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

公开(公告)号：US20190279909A1

公开(公告)日：2019-09-12

申请号：US16416279

申请日：2019-05-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Chun-Hsien Lin ,  Wei-Hao Huang ,  Kai-Teng Cheng

IPC: H01L21/8234 ,  H01L21/30 ,  H01L21/321 ,  H01L21/28

Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.

公开(公告)号：US20190252259A1

公开(公告)日：2019-08-15

申请号：US15893672

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Chun-Hsien Lin ,  Wei-Hao Huang ,  Kai-Teng Cheng

IPC: H01L21/8234 ,  H01L21/30 ,  H01L21/28 ,  H01L21/321

CPC classification number: H01L21/82345 ,  H01L21/28088 ,  H01L21/3003 ,  H01L21/3212 ,  H01L21/823462

Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.

公开(公告)号：US10192825B1

公开(公告)日：2019-01-29

申请号：US15823714

申请日：2017-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hao Huang ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Ying-Chih Lin ,  Chia-Lin Lu

IPC: H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes a first gate line, a second gate line and a first bar-shaped contact structure. The first gate line has a first long axis extending along a first direction. The second gate line is parallel to the first gate line. The first bar-shaped contact structure has a second axis forming an angle substantially greater than 0° and less than 90° with the first long axis.

公开(公告)号：US20180012975A1

公开(公告)日：2018-01-11

申请号：US15677029

申请日：2017-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/26513 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a fin shaped structure, agate structure, an epitaxial layer, an interlayer dielectric layer, a first plug and a protection layer. The fin shaped structure is disposed on a substrate, and the gate structure is across the fin shaped structure. The epitaxial layer is disposed in the fin shaped structure, adjacent to the gate structure. The interlayer dielectric layer covers the substrate and the fin shaped structure. The first plug is formed in the interlayer dielectric layer, wherein the first plug is electrically connected to the epitaxial layer. The protection layer is disposed between the first plug and the gate structure.

公开(公告)号：US09865593B1

公开(公告)日：2018-01-09

申请号：US15402245

申请日：2017-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Hsiang-Hung Peng ,  Wei-Hao Huang ,  Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L27/06 ,  H01L21/8234 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L28/20 ,  H01L28/24

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.

公开(公告)号：US20170133274A1

公开(公告)日：2017-05-11

申请号：US14963216

申请日：2015-12-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Shih-Fang Tzou ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Feng-Yi Chang ,  Wei-Hao Huang

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/31116 ,  H01L21/76897 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL.