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168 条记录 (耗时 0.034 秒)

    Systems and methods for controlling of electro-migration
    31.
    发明申请
    Systems and methods for controlling of electro-migration 有权
    用于控制电迁移的系统和方法

    公开(公告)号：US20060267616A1

    公开(公告)日：2006-11-30

    申请号：US11140765

    申请日：2005-05-31

    申请人： Hayden Cranford ,  Louis Hsu ,  James Mason ,  Chih-Chao Yang

    发明人： Hayden Cranford ,  Louis Hsu ,  James Mason ,  Chih-Chao Yang

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2858 ,  H01L21/76886 ,  H01L2924/0002 ,  H04B7/0814 ,  H01L2924/00

    摘要： Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed.

    摘要翻译： 公开了用于控制电迁移的系统和方法，并减少其有害影响。 实施例提供了当指示电迁移程度的测量指示操作的愈合周期是有必要的时将施加的电压反转到集成电路。 在愈合周期中，集成电路的电路正常工作，但电迁移效应相反。 在一个实施例中，微电子机械开关设置在最低级别的金属化处，以将电流方向切换到集成电路的金属化水平。 在另一个实施例中，如果指示电迁移程度的测量超过参考电平达指定量，则施加到集成电路的电压的极性反转，导致电流切换方向以对抗电迁移。 提供多个开关以切换电流方向通过最低金属化水平，使得即使施加的电压的极性已经被反转，电路也能正常工作。

    Methods to achieve precision alignment for wafer scale packages
    33.
    发明申请
    Methods to achieve precision alignment for wafer scale packages 失效
    实现晶圆级封装精密对准的方法

    公开(公告)号：US20060110852A1

    公开(公告)日：2006-05-25

    申请号：US10994574

    申请日：2004-11-22

    申请人： Howard Chen ,  Louis Hsu

    发明人： Howard Chen ,  Louis Hsu

    IPC分类号： H01L21/48

    CPC分类号： H01L23/5389 ,  H01L21/52 ,  H01L24/83 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2924/1461 ,  H01L2924/00

    摘要： Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed onto a surface of the photoresist layer. The photoresist layer is patterned using the chip as a mask. The chip is removed from the photoresist layer after the patterning step. A pocket is formed in the carrier substrate, and the chip that was removed is placed into the pocket formed in the carrier substrate.

    摘要翻译： 用于制造集成晶片级封装的方法，其减小载体衬底的芯片和凹坑之间的潜在的未对准。 根据本发明的一个方面，一种制造半导体器件的方法包括：设置在载体衬底上的光致抗蚀剂层，放置在光致抗蚀剂层的表面上的芯片。 使用芯片作为掩模对光致抗蚀剂层进行图案化。 在图案化步骤之后，将芯片从光致抗蚀剂层上除去。 在载体基板上形成有袋状物，将被除去的芯片放置在形成于载体基板上的槽内。

    Modified via bottom structure for reliability enhancement
    34.
    发明申请
    Modified via bottom structure for reliability enhancement 有权
    通过底部结构改进可靠性增强

    公开(公告)号：US20060081986A1

    公开(公告)日：2006-04-20

    申请号：US10964882

    申请日：2004-10-14

    申请人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

    发明人： Lawrence Clevenger ,  Timothy Dalton ,  Louis Hsu ,  Conal Murray ,  Carl Radens ,  Kwong-Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01L23/52

    CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.

    摘要翻译： 本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。 本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。 具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

    AUTOMATIC ADAPTIVE EQUALIZATION METHOD AND SYSTEM FOR HIGH-SPEED SERIAL TRANSMISSION LINK
    37.
    发明申请
    AUTOMATIC ADAPTIVE EQUALIZATION METHOD AND SYSTEM FOR HIGH-SPEED SERIAL TRANSMISSION LINK 失效
    用于高速串行传输链路的自动适应均衡方法和系统

    公开(公告)号：US20050281343A1

    公开(公告)日：2005-12-22

    申请号：US10710064

    申请日：2004-06-16

    申请人： Louis Hsu ,  Karl Selander ,  Michael Sorna ,  Jeremy Stephens ,  Huihao Xu

    发明人： Louis Hsu ,  Karl Selander ,  Michael Sorna ,  Jeremy Stephens ,  Huihao Xu

    IPC分类号： H04L25/00 ,  H04L25/03

    CPC分类号： H04L25/03057 ,  H04L25/03343

    摘要： A data communication system includes a transmitter unit and a receiver unit. The transmission unit has a transmission characteristic that is adjustable in accordance with equalization information. The transmission unit is operable to transmit a predetermined signal and the receiver unit is operable to receive the predetermined signal. The receiver unit is further operable to generate the equalization information by examining the eye opening of the received signal, and to transmit the equalization information to the transmitter unit.

    摘要翻译： 数据通信系统包括发射机单元和接收机单元。 发送单元具有根据均衡信息可调的传输特性。 发送单元可操作以发送预定信号，并且接收器单元可操作以接收预定信号。 接收机单元进一步可操作以通过检查接收到的信号的眼图来产生均衡信息，并将均衡信息发送到发射机单元。

    Electronic component value trimming systems
    39.
    发明申请
    Electronic component value trimming systems 失效
    电子元件修整系统

    公开(公告)号：US20050127978A1

    公开(公告)日：2005-06-16

    申请号：US10967756

    申请日：2004-10-18

    申请人： Hayden Cranford ,  Louis Hsu ,  James Mason ,  Gareth Nicholls ,  Philip Murfet ,  Samuel Ray

    发明人： Hayden Cranford ,  Louis Hsu ,  James Mason ,  Gareth Nicholls ,  Philip Murfet ,  Samuel Ray

    IPC分类号： H01C17/22 ,  H03K3/00

    CPC分类号： H01C17/22

    摘要： Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.

    摘要翻译： 描述了一种用于修整电子部件的值的系统。 该系统包括：至少一个修整部件，每个修剪部件具有相关联的开关，用于响应于控制矢量中的对应位选择性地将修剪部件连接到电子部件。 如果电子部件的净值和任何连接的修整部件与期望值不同，则包括比较器以产生具有第一值的输出位。 连接到开关和比较器的控制器根据比较器的输出产生控制向量，该控制器包括用于顺序地从比较器接收连续输出位的移位寄存器; 其中所述控制向量包括所述移位寄存器的内容，并且其中所述控制矢量中的所述第一值的位影响相应开关的切换。