公开(公告)号：US09934185B2

公开(公告)日：2018-04-03

申请号：US14595140

申请日：2015-01-12

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Giulio Corradi

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/00 ,  G06F13/28

CPC classification number: G06F13/4068 ,  G06F13/28

Abstract: In an example, a programmable integrated circuit (IC) includes programmable logic, a processing system, and a network controller. The network controller includes a media access control unit (MAC), a first interface to a physical transceiver, a second interface to the processing system, and a third interface between the MAC and the programmable logic.

公开(公告)号：US09720868B2

公开(公告)日：2017-08-01

申请号：US14325238

申请日：2014-07-07

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Sagheer Ahmad ,  Sarosh I. Azad

IPC: G06F13/364 ,  G06F13/40 ,  G06F12/14 ,  G06F21/78 ,  G06F21/85

CPC classification number: G06F13/404 ,  G06F12/1441 ,  G06F12/145 ,  G06F21/78 ,  G06F21/85

Abstract: Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected, or translated and communicated to the second bus, based on the requester security indicator and the security indicator associated with the address translation information for the requested address. Each access request from the second bus to the first bus includes the requested address, and the access request is translated and communicated to the first bus along with the security indicator that is associated with the address translation information for the requested address.

公开(公告)号：US09529686B1

公开(公告)日：2016-12-27

申请号：US14527469

申请日：2014-10-29

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Sagheer Ahmad

IPC: G01R31/28 ,  G06F11/00 ,  G06F11/30

CPC classification number: G06F11/3027 ,  G06F11/00

Abstract: In an approach for detecting faults on a bus interconnect that connects a bus master circuit to bus slave circuits, application program code and fault detection program code are concurrently executed by a bus master circuit. The application program code initiates first bus transactions to the bus slave circuits, and the fault detection program code initiates second bus transactions to the bus slave circuits for detection of faults in data channels of the bus interconnect. An error code generator circuit generates error codes from addresses of the first and second bus transactions. The error codes are transmitted with the first and second bus transactions on address channels of the bus interconnect to addressed ones of the bus slave circuits. Respective error code checker circuits coupled between the bus interconnect and the bus slave circuits determine whether or not the addresses of the bus transactions are correct based on the error codes.

Abstract translation: 在用于检测将总线主机电路连接到总线从电路的总线互连上的故障的方法中，应用程序代码和故障检测程序代码由总线主机电路同时执行。 应用程序代码向总线从属电路发起第一总线事务，并且故障检测程序代码向总线从电路发起第二总线事务，以检测总线互连的数据通道中的故障。 错误代码生成器电路从第一和第二总线事务的地址生成错误代码。 总线互连的地址信道上的第一和第二总线事务发送到寻址的总线从属电路的错误代码。 耦合在总线互连和总线从属电路之间的各个错误代码校验器电路基于错误代码确定总线事务的地址是否正确。

公开(公告)号：US08937496B1

公开(公告)日：2015-01-20

申请号：US14464661

申请日：2014-08-20

Applicant: Xilinx, Inc.

Inventor： Sagheer Ahmad ,  Alex S. Warshofsky ,  Ygal Arbel

IPC: G01R23/02 ,  H03D3/00 ,  H03K9/06 ,  H03K5/19

CPC classification number: H03K5/19

Abstract: A clock monitoring circuit is disclosed. The clock monitoring circuit is configured to receive first and second clock signals generated in respective clock domains. The clock monitoring circuit includes a first counter configured to count clock cycles of the first clock signal for a first period of time delineated by clock cycles of the second clock signal. The first counter outputs a count value indicating the number of counted clock cycles. The clock monitoring circuit also includes a threshold comparator circuit configured to generate an error signal in response to expiration of the first period of time and the first count value output by the first counter falling outside of an expected range.

Abstract translation: 公开了一种时钟监控电路。 时钟监视电路被配置为接收在各个时钟域中产生的第一和第二时钟信号。 时钟监视电路包括第一计数器，其被配置为对由第二时钟信号的时钟周期描绘的第一时间段对第一时钟信号的时钟周期进行计数。 第一计数器输出指示计数时钟周期数的计数值。 时钟监视电路还包括阈值比较器电路，该阈值比较器电路被配置为响应于第一时间段的期满和由第一计数器输出的第一计数值落在期望范围之外而产生误差信号。

公开(公告)号：US12244518B2

公开(公告)日：2025-03-04

申请号：US17663376

申请日：2022-05-13

Applicant: Xilinx, Inc.

Inventor： Krishnan Srinivasan ,  Sagheer Ahmad ,  Ygal Arbel ,  Aman Gupta

IPC: H04L49/109

Abstract: An integrated circuit (IC) includes a Network-on-Chip (NoC). The NoC includes a plurality of NoC master circuits, a plurality of NoC slave circuits, and a plurality of switches. The plurality of switches are interconnected and communicatively link the plurality of NoC master circuits with the plurality of NoC slave circuits. The plurality of switches are configured to receive data of different widths during operation and implement different operating modes for forwarding the data based on the different widths.

公开(公告)号：US11784149B1

公开(公告)日：2023-10-10

申请号：US17235843

申请日：2021-04-20

Applicant: XILINX, INC.

Inventor： Ygal Arbel ,  Kenneth Ma ,  Balakrishna Jayadev ,  Sagheer Ahmad

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L24/16 ,  H01L23/5384 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/0651 ,  H01L2924/1434

Abstract: Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

公开(公告)号：US11709624B2

公开(公告)日：2023-07-25

申请号：US15898183

申请日：2018-02-15

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Ian A. Swarbrick ,  Sagheer Ahmad

IPC: G06F3/06 ,  G06F13/40 ,  G06F1/28 ,  G06F1/3287

CPC classification number: G06F3/0659 ,  G06F1/28 ,  G06F1/3287 ,  G06F3/0604 ,  G06F3/0634 ,  G06F3/0679 ,  G06F13/4022 ,  G06F2213/0038

Abstract: Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.

公开(公告)号：US10991417B1

公开(公告)日：2021-04-27

申请号：US16422923

申请日：2019-05-24

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel

IPC: G11C11/408 ,  G06F3/06

Abstract: A system includes a queue and a controller. The queue receives a transactions from masters to access a memory component. The memory component includes a plurality of rows. The controller issues a command to access a row of the plurality of rows in response to receiving a first issued transaction. The first issued transaction is issued by a first master. The controller is configured to prevent issuing an auto-precharge command to keep the row associated with the first issued transaction open if a subsequent transaction in the queue from the first master accesses a same row as the first transaction. The controller is configured to prevent issuing the auto-precharge command to keep the row associated with the first issued transaction open if the controller receives data associated with keeping the row associated with the first issued transaction open.

公开(公告)号：US20190391929A1

公开(公告)日：2019-12-26

申请号：US16016349

申请日：2018-06-22

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel ,  Sagheer Ahmad ,  Gaurav Singh

IPC: G06F12/1027 ,  H03K19/177

Abstract: An example programmable integrated circuit (IC) includes a processing system having a processor, a master circuit, and a system memory management unit (SMMU). The SMMU includes a first translation buffer unit (TBU) coupled to the master circuit, an address translation (AT) circuit, an AT interface coupled to the AT circuit, and a second TBU coupled to the AT circuit, and programmable logic coupled to the AT circuit in the SMMU through the AT interface.

公开(公告)号：US10481944B2

公开(公告)日：2019-11-19

申请号：US15673220

申请日：2017-08-09

Applicant: Xilinx, Inc.

Inventor： Ygal Arbel

IPC: G06F9/46 ,  G06F3/06 ,  G06F15/78 ,  G06F11/30 ,  G06F13/16 ,  G06F11/34

Abstract: Disclosed approaches of controlling quality of service in servicing memory transactions includes periodically reading by a quality of service management (QM) circuit, respective first data rate metrics and respective latency metrics from requester circuits while the requester circuits are actively transmitting memory transactions to a memory controller. The QM circuit periodically reads a second data rate metric from the memory controller while the memory controller is processing the memory transactions, and determines, while the requester circuits are actively transmitting memory transactions to the memory controller, whether or not the respective first data rate metrics, respective latency metrics, and second data rate metric satisfy a quality of service metric. In response to determining that the operating metrics do not satisfy the quality of service metric, the QM circuit dynamically changes value(s) of a control parameter(s) of the requester circuit(s) and of the memory controller.