公开(公告)号：US20230161103A1

公开(公告)日：2023-05-25

申请号：US18093981

申请日：2023-01-06

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Wenshi WANG ,  Lina JIANG

IPC: G02B6/122 ,  G02B6/136 ,  G02B6/132

CPC classification number: G02B6/122 ,  G02B6/132 ,  G02B6/136 ,  G02B2006/121

Abstract: A cavity substrate may have a directional optoelectronic transmission channel. The cavity substrate includes a support frame, a first dielectric layer on a first surface of the support frame, and a second dielectric layer on a second surface of the support frame. The support frame, the first dielectric layer and the second dielectric layer constitute a closed cavity having an opening on one side in the length direction of the substrate, a first circuit layer is arranged on the inner surface of the first dielectric layer facing the cavity, an electrode connected with an optical communication device is arranged on the first circuit layer, the electrode is electrically conducted with the first circuit layer, a second circuit layer is arranged on the outer surfaces of the first dielectric layer and the second dielectric layer, and the first circuit layer and the second circuit layer are communicated through a via column.

公开(公告)号：US20230154859A1

公开(公告)日：2023-05-18

申请号：US18099107

申请日：2023-01-19

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Jindong FENG ,  Jiangjiang ZHAO ,  Wenshi WANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/552 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L23/552 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/49838 ,  H01L23/49861

Abstract: Disclosed are a method for manufacturing a support frame structure and a support frame structure. The support frame structure is used for embedded packaging, and includes: a metal plate comprising a support region and an opening region, at least one upper dielectric hole and at least one lower dielectric hole being formed respectively in upper and lower surfaces of the support region, the upper dielectric hole being communicated with the lower dielectric hole; at least one set of metal pillars comprising an upper metal pillar and a lower metal pillar, the upper metal pillar and the lower metal pillar being vertically connected to upper and lower surfaces of the metal plate, respectively; a dielectric layer comprising an upper dielectric layer and a lower dielectric layer, the upper dielectric layer and the lower dielectric layer being correspondingly formed on the upper surface of the metal plate and the upper dielectric hole and on a lower surface of the metal plate and the lower dielectric hole, respectively; and at least one core embedding cavity arranged in the opening region, running through the dielectric layer and the metal plate, and spaced from the upper dielectric hole and the lower dielectric hole by the dielectric layer.

公开(公告)号：US20230127494A1

公开(公告)日：2023-04-27

申请号：US17821725

申请日：2022-08-23

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Yejie HONG ,  Gao HUANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56

Abstract: A signal-heat separated TMV packaging structure includes an insulating dielectric material, an inner signal line layer arranged in the insulating dielectric material, an outer signal line layer, a heat dissipation metal face and a chip. A first side of the insulating dielectric material is provided with an isolating layer. The outer signal line layer is arranged on a surface of a second side of the insulating dielectric material and is connected with the inner signal line layer through a TMV structure. The heat dissipation metal face is arranged on a surface of the first side of the insulating dielectric material, and is separated from the inner signal line layer. The chip is embedded in the insulating dielectric material, with an active face in electrically-conductive connection with the inner signal line layer and a passive face in heat transfer connection with the heat dissipation metal face.

公开(公告)号：US20230010115A1

公开(公告)日：2023-01-12

申请号：US17664417

申请日：2022-05-22

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd.

Inventor： Xianming CHEN ,  Yejie HONG ,  Benxia HUANG ,  Lei FENG

IPC: H01L23/46 ,  H01L21/48

Abstract: A cyclic cooling embedded packaging substrate and a manufacturing method thereof are disclosed. The packaging substrate includes a dielectric material body, a chip, a first metal face, a second metal face and a first trace. The dielectric material body is provided with a packaging cavity, the chip is packaged in the packaging cavity, the first metal face is embedded in the dielectric material body, covers and is connected to a heat dissipation face of the chip. The second metal face is embedded in the dielectric material body, connected to a surface of the first metal face, and is provided with a first cooling channel pattern for forming a cooling channel. The first trace is arranged on a surface of the dielectric material body or embedded therein, and is connected with a corresponding terminal on an active face of the chip through a first conductive structure.

公开(公告)号：US20220068760A1

公开(公告)日：2022-03-03

申请号：US17411144

申请日：2021-08-25

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Benxia HUANG ,  Jindong FENG ,  Minxiong LI ,  Shigui XIN ,  Wenshi WANG

IPC: H01L23/40 ,  H01L23/373

Abstract: A circuit prearranged heat dissipation embedded packaging structure according to an embodiment of the present disclosure includes at least one chip and a support frame surrounding the at least one chip. The support frame may include a via pillar passing through the support frame in the height direction, a first wiring layer on a first surface of the support frame, and a heat dissipation layer on the back face of the chip. The first wiring layer is flush with or higher than the first surface, the first wiring layer is in conductive connection with the heat dissipation layer, a gap between the chip and the frame is completely filled with the dielectric material, a second wiring layer is formed on a terminal face of the chip, and the second wiring layer is in conductive connection with the first wiring layer through the via pillar.

公开(公告)号：US20210407921A1

公开(公告)日：2021-12-30

申请号：US16948518

申请日：2020-09-22

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Jindong FENG ,  Benxia HUANG ,  Lei FENG ,  Jiangjiang ZHAO ,  Wenshi WANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/367 ,  H01L23/552

Abstract: Disclosed are a method for manufacturing a support frame structure and a support frame structure. The method includes steps of: providing a metal plate including a support region and an opening region; forming an upper dielectric hole and a lower dielectric hole respectively at an upper surface and a lower surface of the support region by photolithography, with a metal spacer connected between the upper dielectric hole and the lower dielectric hole; forming an upper metal pillar on an upper surface of the metal plate, and laminating an upper dielectric layer which covers the upper metal pillar and the upper dielectric hole; etching the metal spacer, forming a lower metal pillar on the lower surface of the metal plate, and laminating a lower dielectric layer which covers the lower metal pillar and the lower dielectric hole.

公开(公告)号：US20240186230A1

公开(公告)日：2024-06-06

申请号：US18377399

申请日：2023-10-06

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Xiaowei XU ,  Juchen HUANG ,  Gao HUANG ,  Benxia HUANG

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04026 ,  H01L2224/19 ,  H01L2224/2101

Abstract: A method for manufacturing a component package substrate structure includes providing a first temporary bearing plate, fitting components, applying a first dielectric layer to embed the components in the first dielectric layer, applying a second temporary bearing plate, removing the first temporary bearing plate, forming a connection pad for connecting an element terminal on the first dielectric layer, laminating a second dielectric layer on the first dielectric layer, laminating a circuit board on the second dielectric layer, removing the second temporary bearing plate, opening a stepped hole on the second surface, wherein the stepped hole includes a first via hole penetrating the first dielectric layer, an opening of an annular ring structure of the connection pad and a second via hole penetrating the second dielectric layer, and electroplating the stepped hole to form a conductive column, wherein the conductive column renders the connection pad conductive with the circuit layer.

公开(公告)号：US20240096836A1

公开(公告)日：2024-03-21

申请号：US18221510

申请日：2023-07-13

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Yejie HONG ,  Gao HUANG ,  Benxia HUANG

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L24/20 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L2224/19 ,  H01L2224/24155 ,  H01L2224/244 ,  H01L2924/37

Abstract: A chip high-density interconnection package structure includes a plate having a groove and a glass frame, a first via post penetrating the glass frame, a second via post penetrating the groove, a first line layer and a second line layer on the glass frame and electrically connected via the first via post, a third line layer and a fourth line layer on the groove and electrically connected via the second via post, a chip connection bridge on the third line layer in the groove, and a fifth line layer on the first line layer, and chips on the second line layer and the fourth line layer. The chip connection bridge has a first pad connected to the third line layer, the terminals of the two chips are connected to the fourth line layer and/or the second line layer, and the fifth line layer is connected to the first line layer.

公开(公告)号：US20230309240A1

公开(公告)日：2023-09-28

申请号：US17955855

申请日：2022-09-29

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Xiaowei XU ,  Gao HUANG ,  Benxia HUANG

IPC: H05K3/06 ,  H05K3/00 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K3/064 ,  H05K3/0044 ,  H05K3/4647 ,  H05K1/0298 ,  H05K2203/025 ,  H05K2203/061 ,  H05K2203/143 ,  H05K2203/1446 ,  H05K2201/0376 ,  H05K2201/08

Abstract: A manufacturing method for a conductive substrate with a filtering function includes preparing a core layer and forming first and second conductive holes in the core layer, forming a sacrificial copper layer on the first conductive hole and on the core layer, forming a metal layer on the second conductive hole, forming a metal post in the first conductive hole, forming a lower insulating layer on the core layer, forming a lower insulative post in the second conductive hole, forming a magnet wrapping around the metal post to obtain a first conductive post, forming an upper insulating layer on the core layer, forming an upper insulative post in the second conductive hole to obtain a second conductive post, removing the upper insulating layer, the lower insulating layer, and the remaining sacrificial copper post layer, followed by flattening.

公开(公告)号：US20230282565A1

公开(公告)日：2023-09-07

申请号：US17955759

申请日：2022-09-29

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Xiaowei XU ,  Gao HUANG ,  Benxia HUANG ,  Wenjian LIN

IPC: H01L23/498 ,  H01L25/10 ,  H01L21/48

CPC classification number: H01L23/4985 ,  H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L24/48

Abstract: A packaging structure includes multiple packaging units, and the packaging units include a hard plate region, a winding region, and a fan-out region. In the packaging structure, the hard plate region of the packaging unit is arranged in a stacked manner, some or all of the fan-out regions are packaged with a chip, and some or all of the fan-out regions packaged with a chip are stacked with the hard plate regions after being bent by the winding region. So designed, each fan-out region is individually packaged and then packaged by stacking with each other to achieve the interconnections between a chip and a chip, and between a chip and a substrate without interference between the packaging units.