公开(公告)号：US07764088B2

公开(公告)日：2010-07-27

申请号：US12237025

申请日：2008-09-24

Applicant: Kuan-Yu Chen ,  Wen-Ching Hsiung ,  Cheng-Tao Chang ,  Chia-Liang Lai

Inventor： Kuan-Yu Chen ,  Wen-Ching Hsiung ,  Cheng-Tao Chang ,  Chia-Liang Lai

IPC: H03D13/00

CPC classification number: H03L7/087 ,  H03L7/0807 ,  H03L7/085 ,  H03L7/089

Abstract: A frequency detection circuit and a detection method thereof suitable for a clock data recovery (CDR) circuit are provided. The frequency detection circuit includes a phase detector, a first delayer, a frequency detector, and a logic circuit. The phase detector samples a data signal according to a first clock signal provided by the CDR circuit and provides a phase instruction signal according to the sampling. The first delayer delays the first clock signal to obtain a second clock signal. The frequency detector samples the data signal according to the second clock signal and provides a frequency instruction signal according to the sampling. The logic circuit generates a clock instruction signal according to the phase instruction signal and the frequency instruction signal. The CDR circuit adjusts the frequency of the first clock signal according to the status of the clock instruction signal.

Abstract translation: 提供适用于时钟数据恢复（CDR）电路的频率检测电路及其检测方法。 频率检测电路包括相位检测器，第一延迟器，频率检测器和逻辑电路。 相位检测器根据由CDR电路提供的第一时钟信号对数据信号进行采样，并根据采样提供相位指令信号。 第一延迟器延迟第一时钟信号以获得第二时钟信号。 频率检测器根据第二时钟信号对数据信号进行采样，并根据采样提供频率指令信号。 逻辑电路根据相位指令信号和频率指令信号生成时钟指令信号。 CDR电路根据时钟指令信号的状态来调整第一时钟信号的频率。

公开(公告)号：US07701179B2

公开(公告)日：2010-04-20

申请号：US11760974

申请日：2007-06-11

Applicant: Ke-Horng Chen ,  Yung-Hsin Lin ,  Cheng-Ta Yu

Inventor： Ke-Horng Chen ,  Yung-Hsin Lin ,  Cheng-Ta Yu

IPC: G05F1/24 ,  G05F1/575

CPC classification number: H02M3/1582 ,  H02M3/157 ,  H02M3/1588 ,  Y02B70/1466

Abstract: A control circuit of a multi-mode buck-boost switching regulator and a method thereof are provided. The control circuit imposes ON/OFF timing sequences on switches according to the relationship between two controlling triangle waves and the load fluctuation. In each working cycle of each mode of the regulator, at most two switches perform switching operations. The control circuit is simple to design, which only includes simple digital elements, such as comparators, logic gates etc., instead of complicated analog circuits.

Abstract translation: 提供了多模降压 - 升压开关调节器的控制电路及其方法。 控制电路根据两个控制三角波之间的关系和负载波动对开关施加ON / OFF定时序列。 在调节器的每个模式的每个工作循环中，最多两个开关执行开关操作。 控制电路设计简单，只包括简单的数字元件，比如比较器，逻辑门等，而不是复杂的模拟电路。

公开(公告)号：US07675308B1

公开(公告)日：2010-03-09

申请号：US12195046

申请日：2008-08-20

Applicant: Wang-Chin Chen ,  Chun-Sung Su

Inventor： Wang-Chin Chen ,  Chun-Sung Su

IPC: G01R31/26

CPC classification number: G01R31/3277 ,  G01R31/3187

Abstract: For on-chip testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, after the power switch enters a test mode, the decoupling capacitance is pre-charged or discharged; the power switch is turned ON or OFF according to test patterns; and a voltage level at the decoupling capacitance is analyzed or a leakage current flowing the power switch is measured. So that, whether the power switch is passed or failed is identified.

Abstract translation: 为了片上测试耦合到核心逻辑和去耦电容的片上电源开关，在电源开关进入测试模式之后，去耦电容被预充电或放电; 电源开关根据测试模式打开或关闭; 并且分析去耦电容处的电压电平或测量流过电源开关的漏电流。 确定电源开关是通过还是失败。

公开(公告)号：US07603602B2

公开(公告)日：2009-10-13

申请号：US11563253

申请日：2006-11-27

Applicant: Yeong-Jar Chang

Inventor： Yeong-Jar Chang

IPC: G01R31/28 ,  H03M1/10

CPC classification number: G06F11/24 ,  G01R31/3167

Abstract: A BIST circuit for testing both an analog-to-digital converter and a phase lock loop includes a controllable delay circuit, a NAND gate, a dividing circuit, a NOR gate and a charge/discharge circuit. The invention reduces the period of the signal under test, converts its pulse width to voltage and measures the output via an ADC. The clock jitter becomes sensitive through a delay cancellation method, thus, the accuracy is improved. The invention further comprises all testing procedure for period jitters of a PLL and static characteristics of an ADC. The test error caused by process variation can be corrected by a controllable delay circuit such that the error determination of the test result is prevented.

Abstract translation: 用于测试模数转换器和锁相环的BIST电路包括可控延迟电路，NAND门，分频电路，NOR门和充电/放电电路。 本发明减少被测信号的周期，将其脉冲宽度转换为电压，并通过ADC测量输出。 时钟抖动通过延迟消除方法变得敏感，因此提高了精度。 本发明还包括用于PLL的周期抖动和ADC的静态特性的所有测试程序。 可以通过可控延迟电路校正由过程变化引起的测试误差，从而防止测试结果的错误确定。

公开(公告)号：US07567533B2

公开(公告)日：2009-07-28

申请号：US11380656

申请日：2006-04-28

Applicant: Jyh-Ting Lai

Inventor： Jyh-Ting Lai

IPC: H04Q7/00 ,  H04B17/00

CPC classification number: H04L27/2675 ,  H04L5/023 ,  H04L27/2656 ,  H04W24/00 ,  H04W56/00

Abstract: A packet detector for a multi-band orthogonal frequency division multiplexing system includes a plurality of packet detection units each corresponding to a time frequency code for detecting packets according to a spreading sequence of the time frequency code, a comparison unit for comparing correlation values provided by division units of the plurality of packet detection units, and a packet decision module for determining a time frequency code and size of a fast Fourier transform sampling window according to output signals of the comparison unit, allowing a frequency band to be selected and synchronization to be executed.

Abstract translation: 一种用于多频带正交频分复用系统的分组检测器包括多个分组检测单元，每个分组检测单元分别对应于根据时间频率码的扩展序列检测分组的时间码，比较单元，用于比较由 多个分组检测单元的分割单元，以及分组决定模块，用于根据比较单元的输出信号确定快速傅里叶变换采样窗口的时间码和大小，允许选择频带，同步为 执行。

公开(公告)号：US07548456B2

公开(公告)日：2009-06-16

申请号：US11772299

申请日：2007-07-02

Applicant: Chih-Kang Chiu ,  Wei-Chiang Shih

Inventor： Chih-Kang Chiu ,  Wei-Chiang Shih

IPC: G11C11/34

CPC classification number: G11C11/412 ,  H01L27/105

Abstract: A combo memory cell having a SRAM cell and a mask-ROM code programmer. The SRAM cell comprises first and second inverters. The first inverter comprises a first PMOS transistor and a first NMOS transistor. Gates of the first PMOS and NMOS transistors are commonly connected to a first input node and drains thereof commonly connected to a first output node. The second inverter comprises a second PMOS transistor and a second NMOS transistor. Gates of the second PMOS and NMOS transistors are commonly connected to a second input node and drains thereof commonly connected to a second output node. The first input node and the second output node are connected, as are the second input node and the first output node. The mask-ROM code programmer is coupled to the sources of the first and second PMOS transistors or the first and second NMOS transistors.

Abstract translation: 具有SRAM单元和掩模ROM代码编程器的组合存储单元。 SRAM单元包括第一和第二反相器。 第一反相器包括第一PMOS晶体管和第一NMOS晶体管。 第一PMOS和NMOS晶体管的栅极通常连接到共同连接到第一输出节点的第一输入节点及其下水道。 第二反相器包括第二PMOS晶体管和第二NMOS晶体管。 第二PMOS和NMOS晶体管的栅极通常连接到第二输入节点，并且其通路连接到第二输出节点。 与第二输入节点和第一输出节点一样，连接第一输入节点和第二输出节点。 掩模ROM代码编程器耦合到第一和第二PMOS晶体管或第一和第二NMOS晶体管的源极。

公开(公告)号：US20090134913A1

公开(公告)日：2009-05-28

申请号：US11945053

申请日：2007-11-26

Applicant: Wen-Ching Hsiung ,  Chia-Liang Lai ,  Kuan-Yu Chen ,  Jeng-Dau Chang

Inventor： Wen-Ching Hsiung ,  Chia-Liang Lai ,  Kuan-Yu Chen ,  Jeng-Dau Chang

IPC: G01R19/165

CPC classification number: G01R19/16557 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2200/435 ,  H03F2203/45138 ,  H03F2203/45391 ,  H03F2203/45458 ,  H03F2203/45466 ,  H03K5/082 ,  H03K5/2481

Abstract: A signal comparison circuit is provided. The signal comparison circuit includes a first amplifier, a second amplifier, a peak detector, and a comparator. The first amplifier is a zero-peaking amplifier. The first amplifier receives and amplifies a data signal. The second amplifier receives and amplifies a reference voltage. The peak detector is coupled to the first and the second amplifiers for detecting and maintaining maximum values of the amplified data signal and the amplified reference voltage, and then outputting the maintained data signal and the maintained reference voltage. The comparator is coupled to the peak detector for comparing the maintained data signal with the maintained reference voltage and outputting a result of the comparison.

Abstract translation: 提供信号比较电路。 信号比较电路包括第一放大器，第二放大器，峰值检测器和比较器。 第一个放大器是零峰值放大器。 第一放大器接收并放大数据信号。 第二放大器接收并放大参考电压。 峰值检测器耦合到第一和第二放大器，用于检测和维持放大的数据信号和放大的参考电压的最大值，然后输出维持的数据信号和保持的参考电压。 比较器耦合到峰值检测器，用于将保持的数据信号与维持的参考电压进行比较，并输出比较结果。

公开(公告)号：US20090125763A1

公开(公告)日：2009-05-14

申请号：US11939282

申请日：2007-11-13

Applicant: Yeong-Jar Chang ,  Chung-Fu Lin

Inventor： Yeong-Jar Chang ,  Chung-Fu Lin

IPC: G11C29/08 ,  G06F11/26

CPC classification number: G11C29/16 ,  G01R31/318552 ,  G06F11/2215 ,  G11C29/12015 ,  G11C29/14

Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.

Abstract translation: 提供了可编程存储器内置自检电路及其时钟切换电路。 存储器内置的自检电路能够提供用户预设的更多自检功能，简化了现有技术中的冗余电路，并通过指令解码器和内置的降低芯片面积和降低成本 自检控制器。 本发明还提供了一些存储器的外围控制电路。 控制电路占用的面积较小，能够更灵活地测试存储器。 本发明还提供一种能够在不同时钟速度下正确测试芯片的时钟切换电路，这有利于提高嵌入在芯片中的存储器的可测试性和可分析性，从而增加故障覆盖。

公开(公告)号：US20090122890A1

公开(公告)日：2009-05-14

申请号：US11937007

申请日：2007-11-08

Applicant: Mau-Lin Wu

Inventor： Mau-Lin Wu

IPC: H04L23/02

CPC classification number: H04L27/2649 ,  H04L27/0008 ,  H04L27/0012 ,  H04W52/16

Abstract: An OFDM DCM demodulation method is provided. The OFDM DCM demodulation method mainly includes the following steps. First, calculate a log likelihood of a first demodulation mode. Then calculate a log likelihood of a second demodulation mode. Finally, calculate a demodulation output according to the log likelihoods of the first demodulation mode and the second demodulation mode. The demodulation output may serve as an output of a demodulator of a receiving end of a DCM communication system.

Abstract translation: 提供OFDM DCM解调方法。 OFDM DCM解调方法主要包括以下步骤： 首先，计算第一解调模式的对数似然。 然后计算第二解调模式的对数似然。 最后，根据第一解调模式和第二解调模式的对数似然度来计算解调输出。 解调输出可以用作DCM通信系统的接收端的解调器的输出。

公开(公告)号：US20090089548A1

公开(公告)日：2009-04-02

申请号：US11862816

申请日：2007-09-27

Applicant: I-Jui Sung ,  Ming-Chung Kao

Inventor： I-Jui Sung ,  Ming-Chung Kao

IPC: G06F9/30

CPC classification number: G06F9/383 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/3832

Abstract: A method for preloading data in a CPU pipeline is provided, which includes the following steps. When a hint instruction is executed, allocate and initiate an entry in a preload table. When a load instruction is fetched, load a piece of data from a memory into the entry according to the entry. When a use instruction which uses the data loaded by the load instruction is executed, forward the data for the use instruction from the entry instead of from the memory. When the load instruction is executed, update the entry according to the load instruction.

Abstract translation: 提供了一种在CPU流水线中预加载数据的方法，包括以下步骤。 执行提示指令时，在预载表中分配并启动一个条目。 当读取加载指令时，根据条目将一条数据从存储器加载到条目中。 当使用使用由加载指令加载的数据的使用指令执行时，将来自条目的使用指令的数据转发到存储器中。 执行加载指令时，根据加载指令更新条目。