公开(公告)号：US20050242383A1

公开(公告)日：2005-11-03

申请号：US11175451

申请日：2005-07-07

申请人： Takumi Mikawa

发明人： Takumi Mikawa

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11509 ,  H01L21/28568 ,  H01L21/76895 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

摘要： A capacitor upper electrode and a wiring are electrically connected to each other by using a plug and a conductive layer formed below a capacitive element without using a plug that directly connects the capacitor upper electrode to the wiring provided thereon via an interlayer insulating film therebetween. Alternatively, the capacitor upper electrode is covered by a conductive hydrogen barrier film, and the capacitor upper electrode and the wiring are electrically connected to each other via both a plug connecting the wiring and the conductive hydrogen barrier film to each other and the conductive hydrogen barrier film.

公开(公告)号：US20050239251A1

公开(公告)日：2005-10-27

申请号：US11169040

申请日：2005-06-29

申请人： Toyoji Ito ,  Eiji Fujii ,  Kazuo Umeda

发明人： Toyoji Ito ,  Eiji Fujii ,  Kazuo Umeda

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11502 ,  H01L27/105 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55 ,  H01L28/57 ,  H01L28/65

摘要： A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.

摘要翻译： 半导体器件包括：下阻氢膜; 形成在下部氢阻挡膜上并具有下部电极，电容绝缘膜和上部电极的电容器; 形成为覆盖电容器周围的层间绝缘膜; 以及覆盖电容器的顶部和侧部的上部氢阻挡膜。 在层间电介质膜中形成开口，该开口暴露出下阻氢膜位于电容器周围并在其间呈锥形并向上凸起的下阻氢膜，上阻氢膜沿着 开口的侧面和底面，并与开口中的下阻氢膜接触。

公开(公告)号：US20050162946A1

公开(公告)日：2005-07-28

申请号：US11038526

申请日：2005-01-21

申请人： Yasunori Koide

发明人： Yasunori Koide

IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C8/12 ,  H01L23/12 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/10 ,  H01L27/105

CPC分类号： H01L25/0657 ,  G11C5/02 ,  G11C8/12 ,  G11C11/22 ,  H01L27/105 ,  H01L27/11509 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide laminated type semiconductor memory devices that can improve the yield of chips without complicating wirings and components. There are provided a plurality of laminated semiconductor chip layers, and chip selection pads provided on each of the chip layers, which are mutually connected across the chip layers, respectively, such that a chip selection signal for selecting each of the chip layers is commonly inputted in each of the chip layers. Each of the chip layers is equipped with program circuits each of which is capable of programming an output signal, and a chip selection judging circuit that judges a chip selection based on the chip selection signal and an output signal of the program circuit. As a result, address information can be set afterwards by the program circuit, such that one kind of chips may suffice in the chip manufacturing stage. Because the chip selection signal is inputted in the common chip selection pads, independent wirings for the respective chips are not required.

摘要翻译： 提供层叠型半导体存储器件，其可以提高芯片的产量而不会使配线和部件复杂化。 分别设置多个叠层半导体芯片层和设置在每个芯片层上的芯片选择焊盘，其分别相互连接在芯片层之间，使得用于选择每个芯片层的芯片选择信号被共同输入 在每个芯片层中。 每个芯片层配备有能够编程输出信号的编程电路，以及基于芯片选择信号和程序电路的输出信号来判断芯片选择的芯片选择判断电路。 结果，可以由程序电路随后设置地址信息，使得一种芯片在芯片制造阶段就足够了。 由于芯片选择信号被输入到公共芯片选择焊盘中，因此不需要各自芯片的独立布线。

公开(公告)号：US20020149045A1

公开(公告)日：2002-10-17

申请号：US10164409

申请日：2002-06-10

申请人： MATSUSHITA ELECTRONICS CORPORATION

发明人： Yoshihisa Nagano ,  Yusuhiro Uemoto

IPC分类号： H01L029/94

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

摘要： A protective insulating film is deposited over first and second field-effect transistors formed on a semiconductor substrate. A capacitor composed of a capacitor lower electrode, a capacitor insulating film composed of an insulating metal oxide film, and a capacitor upper electrode is formed on the protective insulating film. A first contact plug formed in the protective insulating film provides a direct connection between the capacitor lower electrode and an impurity diffusion layer of the first field-effect transistor. A second contact plug formed in the protective insulating film provides a direct connection between the capacitor upper electrode and an impurity diffusion layer of the second field-effect transistor.

摘要翻译： 保护绝缘膜沉积在形成在半导体衬底上的第一和第二场效应晶体管上。 在保护绝缘膜上形成由电容器下电极构成的电容器，由绝缘金属氧化物膜构成的电容绝缘膜和电容器上电极。 形成在保护绝缘膜中的第一接触插塞提供电容器下电极和第一场效应晶体管的杂质扩散层之间的直接连接。 形成在保护绝缘膜中的第二接触插塞提供电容器上电极和第二场效应晶体管的杂质扩散层之间的直接连接。

公开(公告)号：US06458602B1

公开(公告)日：2002-10-01

申请号：US09889855

申请日：2001-07-23

申请人： Takashi Yunogami ,  Kenichi Shoji

发明人： Takashi Yunogami ,  Kenichi Shoji

IPC分类号： H01L2100

CPC分类号： H01L27/11507 ,  H01L21/31138 ,  H01L21/32136 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11509 ,  H01L28/55

摘要： According to the invention of the present application, for providing an etching technique for a wiring layer capable of decreasing the degradation of characteristics of a ferroelectric film in FeRAM, a wiring material (LI wiring 18, Al wiring 30) connected with an electrode layer of a ferroelectric film 11 (lower electrode 10, upper electrode 12) is fabricated by dry etching using inducely coupled plasma upon forming the wiring layer and, successively, applied with an asher treatment at a temperature of 300° C. or higher by using inducely coupled plasma while introducing a gas mixture, for example, of O2+CF4+H2O.

摘要翻译： 根据本申请的发明，为了提供能够降低FeRAM中的铁电体膜的特性劣化的布线层的蚀刻技术，可以将与电极层的电极层连接的布线材料（LI布线18，Al布线30） 通过在形成布线层时使用诱导耦合等离子体进行干法蚀刻制造铁电体膜11（下电极10，上电极12），并且通过使用诱导耦合的方式在300℃以上的温度下进行灰处理 同时引入例如O 2 + CF 4 + H 2 O的气体混合物。

公开(公告)号：US06218197B1

公开(公告)日：2001-04-17

申请号：US09606452

申请日：2000-06-29

申请人： Naoki Kasai

发明人： Naoki Kasai

IPC分类号： H01G706

CPC分类号： H01L27/11502 ,  H01L27/105 ,  H01L27/11507 ,  H01L27/11509

摘要： An embedded LSI includes a FeRAM macro block and an associated logic circuit section. A hydrogen barrier layer covers the FeRAM macro block as a whole and exposes the logic circuit section. The edge of the hydrogen barrier layer overlies the peripheral circuit of the FeRAM macro block and the boundary separating the FeRAM macro block from the logic circuit section. The ferroelectric capacitor is protected by the hydrogen barrier layer against hydrogen during a hydrogen-annealing process.

摘要翻译： 嵌入式LSI包括FeRAM宏块和相关联的逻辑电路部分。 氢阻挡层整体覆盖FeRAM宏块并使逻辑电路部分露出。 氢阻挡层的边缘覆盖FeRAM宏块的外围电路和将FeRAM宏块与逻辑电路部分分离的边界。 在氢退火过程中，强电介质电容器被氢阻挡层与氢气保护。

公开(公告)号：US10074414B2

公开(公告)日：2018-09-11

申请号：US15679016

申请日：2017-08-16

申请人： MICRON TECHNOLOGY, INC.

发明人： Scott J. Derner ,  Christopher J. Kawamura

IPC分类号： G11C11/22 ,  H01L27/11514 ,  H01L27/11509

CPC分类号： G11C11/2257 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  H01L27/11509 ,  H01L27/11514

摘要： Apparatuses and methods are disclosed that in ferroelectric memory and for operating ferroelectric memory. An example apparatus includes a capacitor having a first plate, a second plate, and a ferroelectric dielectric material. The apparatus further includes a first digit line and a first selection component configured to couple the first plate to the first digit line, and also includes a second digit line and a second selection component configured to couple the second plate to the second digit line.

公开(公告)号：US09349842B2

公开(公告)日：2016-05-24

申请号：US13793645

申请日：2013-03-11

申请人： GLOBALFOUNDRIES Inc.

发明人： Till Schloesser ,  Peter Baars

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/51 ,  H01L27/115 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L29/6684 ,  H01L21/28291 ,  H01L21/823462 ,  H01L27/11509 ,  H01L29/516 ,  H01L29/78391

摘要： Ferroelectric circuit elements, such as field effect transistors or capacitors, may be formed on the basis of hafnium oxide, which may also be used during the fabrication of sophisticated high-k metal gate electrode structures of fast transistors. To this end, the hafnium-based oxide having appropriate thickness and material composition may be patterned at any appropriate manufacturing stage, without unduly affecting the overall process flow for fabricating a sophisticated high-k metal gate electrode structure.

摘要翻译： 可以在氧化铪的基础上形成诸如场效应晶体管或电容器的铁电电路元件，其也可以在制造快速晶体管的复杂高k金属栅电极结构期间使用。 为此，可以在任何合适的制造阶段对具有适当厚度和材料组成的铪基氧化物进行图案化，而不会不利地影响用于制造复杂的高k金属栅电极结构的整个工艺流程。

公开(公告)号：US09305996B2

公开(公告)日：2016-04-05

申请号：US14310407

申请日：2014-06-20

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Kouichi Nagai

IPC分类号： H01L21/02 ,  H01L49/02 ,  H01L27/115

CPC分类号： H01L28/60 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L28/55

摘要： After the formation of a first interlayer insulating, an etching stopper film made of SiON is formed thereon. Subsequently, a contact hole extending from the upper surface of the etching stopper film and reaching a high concentration impurity region is formed, and a first plug is formed by filling W into the contact hole. Next, a ferroelectric capacitor, a second interlayer insulating film, and the like are formed. Thereafter, a contact hole extending from the upper surface of the interlayer insulating film and reaching the first plug is formed. Then, the contact hole is filled with W to form a second plug. With this, even when misalignment occurs, the interlayer insulating film is prevented from being etched.

摘要翻译： 在形成第一层间绝缘之后，在其上形成由SiON制成的蚀刻阻挡膜。 随后，形成从蚀刻阻止膜的上表面延伸并达到高浓度杂质区的接触孔，并且通过将W填充到接触孔中而形成第一插塞。 接下来，形成铁电电容器，第二层间绝缘膜等。 此后，形成从层间绝缘膜的上表面延伸并到达第一插塞的接触孔。 然后，接触孔填充有W以形成第二插头。 由此，即使发生不对准，也可以防止层间绝缘膜被蚀刻。

公开(公告)号：US20150060969A1

公开(公告)日：2015-03-05

申请号：US14464952

申请日：2014-08-21

申请人： FUJITSU SEMICONDUCTOR LIMITED

发明人： Osamu Matsuura

IPC分类号： G11C11/22 ,  H01L43/12 ,  H01L27/22

CPC分类号： G11C11/221 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/11509 ,  H01L29/516 ,  H01L2924/1441

摘要： A semiconductor device includes a transistor formed on a semiconductor substrate, a first insulation film formed above the semiconductor substrate, and first and second capacitors located on the first insulation film. The first capacitor includes a lower electrode, a ferroelectric, and an upper electrode. One of the lower electrode and the upper electrode is connected to an impurity region of the transistor. The second capacitor includes a first electrode, a first dielectric, a second electrode, a second dielectric, and a third electrode. The lower electrode is formed from the same material as the first electrode, the ferroelectric is formed from the same material as the first dielectric, and the upper electrode is formed from the same material as the second electrode.

摘要翻译： 半导体器件包括形成在半导体衬底上的晶体管，形成在半导体衬底上的第一绝缘膜，以及位于第一绝缘膜上的第一和第二电容器。 第一电容器包括下电极，铁电体和上电极。 下电极和上电极中的一个连接到晶体管的杂质区。 第二电容器包括第一电极，第一电介质，第二电极，第二电介质和第三电极。 下电极由与第一电极相同的材料形成，铁电体由与第一电介质相同的材料形成，并且上电极由与第二电极相同的材料形成。