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31.发明授权公开(公告)号：US12058865B2
公开(公告)日：2024-08-06
申请号：US17117714
申请日：2020-12-10
发明人： Zhong Zhang , Yuhui Han , Wenxi Zhou
CPC分类号： H10B43/50 , H01L23/562 , H10B41/27 , H10B41/50 , H10B43/27
摘要： A 3D memory device includes a memory stack and a support structure. The memory stack, on a substrate, includes a core region and a non-core region neighboring the core region. The support structure extends in the non-core region and into the substrate. The support structure includes a first support portion and a second support portion over the first support portion. The first support portion has a stiffness higher than the second support portion.
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公开(公告)号：US20240233824A1
公开(公告)日：2024-07-11
申请号：US18614908
申请日：2024-03-25
发明人： Myunghun LEE , Sangwan NAM , Taemin OK
IPC分类号： G11C16/04 , G11C16/26 , H01L23/528 , H10B41/27 , H10B41/40 , H10B41/50 , H10B43/10 , H10B43/20 , H10B43/27 , H10B43/40 , H10B43/50
CPC分类号： G11C16/0483 , G11C16/26 , H01L23/528 , H10B41/27 , H10B41/40 , H10B41/50 , H10B43/10 , H10B43/20 , H10B43/27 , H10B43/40 , H10B43/50
摘要： An integrated circuit device includes a peripheral circuit structure including a lower substrate, an arc protection diode in the lower substrate, and a common source line driver connected to the arc protection diode, a conductive plate on the peripheral circuit structure, a cell array structure overlapping the peripheral circuit structure in a vertical direction with the conductive plate therebetween, and a first wiring structure connected between the arc protection diode and the conductive plate.
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公开(公告)号：US12021022B2
公开(公告)日：2024-06-25
申请号：US17645866
申请日：2021-12-23
发明人： Geunwon Lim
摘要： A semiconductor device includes a substrate having a cell array region and a pad region, a stack structure including gate electrodes and mold insulating layers alternately stacked on the substrate and having a staircase shape in the pad region, first separation regions penetrating the stack structure in the pad region, extending in a first direction, and including first and second dummy insulating layers, the first dummy insulating layers covering side walls of the first separation regions and including horizontal portions covering portions of the gate electrodes, and the second dummy insulating layers disposed between the first dummy insulating layers, extending portions extending towards the mold insulating layers from the first dummy insulating layers in a second direction perpendicular to the first direction, second separation regions dividing the stack structure and extending in the first direction, and cell contact plugs penetrating the horizontal portions and connected to the gate electrodes.
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34.发明授权公开(公告)号：US12014966B2
公开(公告)日：2024-06-18
申请号：US18115810
申请日：2023-03-01
发明人： Sheng-Chieh Chen , Wei-Ming Wang , Ming-Lun Lee , Chih-Ren Hsieh , Ming Chyi Liu
IPC分类号： H01L27/11524 , H01L21/28 , H01L21/56 , H01L23/29 , H01L23/31 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/788 , H10B41/35 , H10B41/41 , H10B41/43 , H10B41/50
CPC分类号： H01L23/291 , H01L21/56 , H01L23/3192 , H01L29/40114 , H01L29/41775 , H01L29/42328 , H01L29/66825 , H01L29/788 , H10B41/35 , H10B41/41 , H10B41/43 , H10B41/50
摘要： A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.
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公开(公告)号：US20240147725A1
公开(公告)日：2024-05-02
申请号：US18408864
申请日：2024-01-10
申请人： Kioxia Corporation
发明人： Shinya ARAI
IPC分类号： H10B43/27 , G11C16/14 , H01L21/764 , H01L29/06 , H10B41/27 , H10B41/35 , H10B41/50 , H10B43/35 , H10B43/40 , H10B43/50
CPC分类号： H10B43/27 , G11C16/14 , H01L21/764 , H01L29/0649 , H10B41/27 , H10B41/35 , H10B41/50 , H10B43/35 , H10B43/40 , H10B43/50 , G11C16/0483
摘要： According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
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公开(公告)号：US11895837B2
公开(公告)日：2024-02-06
申请号：US17737164
申请日：2022-05-05
发明人： Janggn Yun , Jaeduk Lee
摘要： A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes stacked on the substrate, a channel structure penetrating the plurality of gate electrodes and including a channel layer extending in a vertical direction perpendicular to an upper surface of the substrate in the memory cell region, a dummy channel structure penetrating the plurality of gate electrodes and including a dummy channel layer extending in the vertical direction in the connection region, a first semiconductor layer disposed between the substrate and a lowermost one of the plurality of gate electrodes and surrounding the channel structure in the memory cell region, and an insulating separation structure disposed between the substrate and the lowermost one of the plurality of gate electrodes and surrounding the dummy channel layer.
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公开(公告)号：US11864382B2
公开(公告)日：2024-01-02
申请号：US17073786
申请日：2020-10-19
发明人： Jongwon Kim , Young-Jin Jung
摘要： A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.
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公开(公告)号：US11864381B2
公开(公告)日：2024-01-02
申请号：US17567613
申请日：2022-01-03
发明人： Meng-Han Lin , Chih-Ren Hsieh , Ching-Wen Chan
摘要： In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.
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公开(公告)号：US11839084B2
公开(公告)日：2023-12-05
申请号：US17825619
申请日：2022-05-26
发明人： Euntaek Jung , JoongShik Shin , JiHye Yun
IPC分类号： H10B43/27 , H01L21/768 , H01L23/528 , H01L23/532 , H01L21/285 , H01L21/28 , H10B41/27 , H10B41/35 , H10B41/41 , H10B43/35 , H10B43/40 , H01L23/522 , H10B41/50 , H10B43/50 , H10B69/00 , H01L29/66 , H10B43/30
CPC分类号： H10B43/27 , H01L21/28525 , H01L21/76868 , H01L23/528 , H01L23/53271 , H01L29/40114 , H01L29/40117 , H10B41/27 , H10B41/35 , H10B41/41 , H10B43/35 , H10B43/40 , H01L23/5226 , H01L23/5283 , H01L29/66833 , H10B41/50 , H10B43/30 , H10B43/50 , H10B69/00
摘要： A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.
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公开(公告)号：US20230247829A1
公开(公告)日：2023-08-03
申请号：US18132019
申请日：2023-04-07
发明人： Junhyoung KIM , Jisung CHEON
摘要： A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern.
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