公开(公告)号：US20240144991A1

公开(公告)日：2024-05-02

申请号：US18326657

申请日：2023-05-31

申请人： Samsung Electronics Co., Ltd.

发明人： Jaewoo JEONG ,  Yonghun KIM ,  Kihan KIM ,  Changsik YOO

IPC分类号： G11C11/4076 ,  G06F1/10 ,  G06F1/12

CPC分类号： G11C11/4076 ,  G06F1/10 ,  G06F1/12

摘要： A memory device includes a multi-phase clock generator configured to generate first to N-th clock signals having N different phases based on a clock signal from the memory controller, and a monitoring clock signal generator configured to generate a monitoring clock signal having a logic state corresponding to a data pattern in synchronization with edges of the first to N-th clock signals, wherein the monitoring clock signal includes a first monitoring clock signal configured to detect a skew between the first and third clock signals in a first step of a training operation, a second monitoring clock signal configured to detect a skew between the second and fourth clock signals in a second step of the training operation, and a third monitoring clock signal configured to detect a skew between the first and second clock signals in a third step of the training operation.

公开(公告)号：US11971741B2

公开(公告)日：2024-04-30

申请号：US17396046

申请日：2021-08-06

申请人： QUALCOMM Incorporated

发明人： Mukund Narasimhan ,  Murali Krishna Ade ,  Arun David Arul Diraviyam ,  Mayank Gupta ,  Boris Dimitrov Andreev

IPC分类号： G06F1/10 ,  G06F1/12 ,  G06F9/30 ,  G06F9/54

CPC分类号： G06F1/10 ,  G06F1/12 ,  G06F9/30134 ,  G06F9/544

摘要： Aspects of the present disclosure control aging of a signal path in an idle mode to mitigate aging. In one example, an input of the signal path is alternately parked low and high over multiple idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, a clock signal (e.g., a clock signal with a low frequency) is input to the signal path during idle periods to balance the aging of devices (e.g., transistors) in the signal path. In another example, the input of the signal path is parked high or low during each idle period based on an aging pattern.

公开(公告)号：US11966252B2

公开(公告)日：2024-04-23

申请号：US17769011

申请日：2020-10-15

申请人： BP Exploration Operating Company Limited

发明人： Alistair George Crosby

IPC分类号： G06F1/00 ,  G06F1/12 ,  G06F1/14 ,  G06F1/10

CPC分类号： G06F1/14 ,  G06F1/12 ,  G06F1/10

摘要： In some examples, the disclosure provides a method for determining a drift in clock data that is provided by a clock of a seismic sensor. The sensor is exposed to an ambient temperature that varies over time. The method includes obtaining temperature data associated with the ambient temperature as a function of time. The method also includes obtaining the clock data. The method also includes obtaining timestamp data provided by a global navigation satellite system. The method also includes determining drift data which minimizes a difference of a temporal drift in the clock data, based on the timestamp data and the temperature data. The method also includes outputting corrective data based on the determined drift data.

公开(公告)号：US11960906B2

公开(公告)日：2024-04-16

申请号：US18048588

申请日：2022-10-21

申请人： Micron Technology, Inc.

发明人： Hyunui Lee

IPC分类号： G06F9/445 ,  G06F3/06 ,  G06F13/20 ,  G11C7/10 ,  G11C11/4093 ,  G06F1/10

CPC分类号： G06F9/44505 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/20 ,  G11C7/1048 ,  G11C11/4093 ,  G06F1/10

摘要： A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.

公开(公告)号：US20240119993A1

公开(公告)日：2024-04-11

申请号：US18390431

申请日：2023-12-20

申请人： Advanced Micro Devices, Inc.

发明人： Aaron John Nygren ,  Kathik Gopalakrishnan ,  Tsun Ho Liu

IPC分类号： G11C11/4076 ,  G06F1/08 ,  G06F1/10 ,  G06F3/06

CPC分类号： G11C11/4076 ,  G06F1/08 ,  G06F1/10 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0671

摘要： A memory controller monitors memory command selected for dispatch to the memory and sends commands controlling a read clock state. A memory includes a read clock circuit and a mode register. The read clock circuit has an output for providing a hybrid read clock signal in response to a clock signal and a read clock mode signal. The read clock circuit provides the hybrid read clock signal as a free-running clock signal that toggles continuously, and as a strobe signal that is active only in response to the memory receiving a read command.

公开(公告)号：US11953936B2

公开(公告)日：2024-04-09

申请号：US17513004

申请日：2021-10-28

申请人： Silicon Laboratories Inc.

发明人： Eugenio Carey

IPC分类号： H03K5/135 ,  G01R31/28 ,  G06F1/10 ,  G06F9/445

CPC分类号： G06F1/10 ,  G01R31/2896 ,  G06F9/445 ,  H03K5/135

摘要： In one embodiment, an apparatus includes: an oscillator to output a clock signal on a first line; a switch coupled to the first line; and a voltage divider coupled to the switch. The switch may be controlled to output the clock signal through the voltage divider via the first line to a pin in a non-reset mode and prevent the clock signal from being provided to the pin in a reset mode.

公开(公告)号：US20240111444A1

公开(公告)日：2024-04-04

申请号：US17958108

申请日：2022-09-30

申请人： Intel Corporation

发明人： Javier MARTIN LANGERWERF ,  Jeroen LEIJTEN ,  Gerard EGELMEERS ,  Venkata Sudhir KONJETI

IPC分类号： G06F3/06 ,  G06F1/10

CPC分类号： G06F3/064 ,  G06F1/10 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0673

摘要： Examples include techniques to reduce power consumption for a distributed computational model mapped onto a multi-processing node system. Examples are described of processing nodes relaying indicator information to enable clock gate circuitry to determine whether or not to gate a clock to stall consuming compute circuitry based on availability of data to consume. Examples are also described of processing nodes relaying indicator information to enable clock gate circuitry to determine whether or not to gate a clock to stall producing compute circuitry based on available buffer capacity at a consuming compute circuitry.

公开(公告)号：US20240103561A1

公开(公告)日：2024-03-28

申请号：US17953503

申请日：2022-09-27

申请人： ATI TECHNOLOGIES ULC

发明人： Erwin PANG

IPC分类号： G06F1/10

CPC分类号： G06F1/10

摘要： A method for clock distribution network control includes determining, at a first clock node of a plurality of clock nodes within a clock distribution network, a downstream clock request status. A clock request signal is transmitted by the first clock node to an upstream parent node based on the downstream clock request status. A clock buffer of the first clock node is toggled based at least in part on the clock request signal to the parent node. If the first clock node receives an asserted clock request signal from one or more downstream child nodes and clock acknowledgment signal from the parent node, a clock enable signal is asserted to the clock buffer to output a clock signal to the one or more downstream child nodes.

公开(公告)号：US20240103560A1

公开(公告)日：2024-03-28

申请号：US17766254

申请日：2020-11-20

申请人： Hajime TSUKAHARA ,  Tomohiro SASA

发明人： Hajime TSUKAHARA ,  Tomohiro SASA

IPC分类号： G06F1/10

CPC分类号： G06F1/10

摘要： A data processing device comprises: a data receiver to receive data to be processed, an external clock, and a unit control signal determining a processing unit for the data to be processed from an outside, the data receiver including a PLL circuit to receive the external clock; a clock abnormality detector to operate based on a clock of a system different from a system of the external clock and detect abnormality of the external clock based on a lock signal output from the PLL circuit; and a data processing controller to control processing of the data. When abnormality of the external clock is detected, the data processing controller stops taking in the data to be processed, and when the external clock becomes normal again, take in the unit control signal and resume taking in the data to be processed.

公开(公告)号：US11928072B2

公开(公告)日：2024-03-12

申请号：US17685982

申请日：2022-03-03

申请人： Kioxia Corporation

发明人： Hiroshi Tsurumi

IPC分类号： G06F13/42 ,  G06F1/10

CPC分类号： G06F13/4221 ,  G06F1/10 ,  G06F2213/0026

摘要： A controller includes a physical layer interface circuit configured to support a first port and a second port both conforming to a PCIe standard, the first port including a first number of lanes with a first order, the second port including a second number of lanes with a second order, and the first number of lanes and the second number of lanes being connected to the physical layer interface circuit via traces arranged in an order in which at least a part of the first order and at least a part of the second order are changed based on Lane Reversal conforming to the PCIe standard.