公开(公告)号：US12135981B2

公开(公告)日：2024-11-05

申请号：US18207870

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US12135780B2

公开(公告)日：2024-11-05

申请号：US18232810

申请日：2023-08-10

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Jason W. Brandt ,  Ravi L. Sahita ,  Barry E. Huntley ,  Baiju V. Patel ,  Deepak K. Gupta

IPC: G06F21/52 ,  G06F3/06 ,  G06F9/30 ,  G06F9/46 ,  G06F12/14

Abstract: A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.

公开(公告)号：US12135667B2

公开(公告)日：2024-11-05

申请号：US18327043

申请日：2023-05-31

Applicant: Intel Corporation

Inventor： Jeffrey Erik Schulz ,  David W. Mendel ,  Dinesh D. Patil ,  Gary Brian Wallichs ,  Keith Duwel ,  Jakob Raymond Jones

IPC: H01L25/065 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  H01L23/00 ,  H01L23/498 ,  H03K19/173 ,  H04W56/00

Abstract: An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

公开(公告)号：US12135597B2

公开(公告)日：2024-11-05

申请号：US16886694

申请日：2020-05-28

Applicant: Intel Corporation

Inventor： Ang Li

IPC: G06F1/32 ,  G06F1/14 ,  G06F1/3206 ,  G06F1/324 ,  G06F9/46 ,  G06F13/38

Abstract: Systems and devices can include power management circuitry to manage the entry and exit of active state power management (APSM) link states, such as the transition between an active (L0) state and a low power state (e.g., L1). The power management circuitry can cause a downstream component to initiate an ASPM link state change negotiation based on an ASPM link state change condition being met. An ASPM event analysis logic can identify and track events that occur proximate in time to the ASPM link state change and can correlate the occurrences of the event with ASPM link state changes. An ASPM policy tuning logic can use a correlation between the occurrences of the event and ASPM link state changes to adjust or tune the ASPM link state change condition.

公开(公告)号：US12135569B2

公开(公告)日：2024-11-05

申请号：US17133279

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Rodrigo De Oliveira Vivi ,  John Kelbert ,  David Lombard ,  Eric Moret ,  Mark Luckeroth ,  Brad Bittel ,  Phani Kumar Kandula

IPC: G05D23/19 ,  G05B15/02 ,  G06F9/48 ,  G06F9/50

Abstract: Methods, apparatus, systems, and articles of manufacture to reduce thermal fluctuations in semiconductor processors are disclosed. An apparatus includes a temperature analyzer to determine a current temperature of a processor. The apparatus further includes a controller to provide an idle workload to the processor to execute in response to the current temperature falling below a setback temperature.

公开(公告)号：US20240364002A1

公开(公告)日：2024-10-31

申请号：US18139206

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Thomas Wagner ,  Bernd Waidhas ,  Georg Seidemann ,  Tae Young Yang ,  Telesphor Kamgaing

IPC: H01Q1/50 ,  H01Q1/22 ,  H01Q9/04

CPC classification number: H01Q1/50 ,  H01Q1/2283 ,  H01Q9/045

Abstract: An antenna device includes integrated polymer nanocomposite (PNC) devices coupling an antenna on a substrate to both ground and signal terminals. The PNC devices may include PNC material between two electrodes. The PNC devices may be integrated into the antenna device with the substrate including at least one electrode of each of the PNC devices. One PNC device may convey a signal to or from the antenna, e.g., between the antenna and a signal terminal. Another PNC device may convey an electrostatic discharge (ESD) pulse to a ground terminal. The antenna device may include or be coupled to an integrated circuit (IC) die. The IC die may couple to the signal and ground terminals, e.g., opposite the substrate from the antenna.

公开(公告)号：US20240363628A1

公开(公告)日：2024-10-31

申请号：US18767458

申请日：2024-07-09

Applicant: Intel Corporation

Inventor： Leonard P. GULER ,  William HSU ,  Biswajeet GUHA ,  Martin WEISS ,  Apratim DHAR ,  William T. BLANTON ,  John H. IRBY, IV ,  James F. BONDI ,  Michael K. HARPER ,  Charles H. WALLACE ,  Tahir GHANI ,  Benedict A. SAMUEL ,  Stefan DICKERT

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0886 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/78696

Abstract: Gate-all-around integrated circuit structures having adjacent island structures are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A first vertical arrangement of horizontal nanowires is above a first fin protruding from the semiconductor substrate. A channel region of the first vertical arrangement of horizontal nanowires is electrically isolated from the fin. A second vertical arrangement of horizontal nanowires is above a second fin protruding from the semiconductor substrate. A channel region of the second vertical arrangement of horizontal nanowires is electrically isolated from the second fin. The semiconductor island is between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires.

公开(公告)号：US20240362391A1

公开(公告)日：2024-10-31

申请号：US18769148

申请日：2024-07-10

Applicant: Intel Corporation

Inventor： Ranjith KUMAR ,  Quan SHI ,  Mark T. BOHR ,  Andrew W. YEOH ,  Sourav CHAKRAVARTY ,  Barbara A. CHAPPELL ,  M. Clair WEBB

IPC: G06F30/392 ,  G06F30/20 ,  G06F30/337 ,  G06F30/347 ,  G06F30/373 ,  G06F30/3947 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118

CPC classification number: G06F30/392 ,  G06F30/337 ,  G06F30/347 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11807 ,  G06F30/20 ,  G06F30/373 ,  G06F30/3947 ,  H01L2027/11875

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

公开(公告)号：US20240361541A1

公开(公告)日：2024-10-31

申请号：US18309123

申请日：2023-04-28

Applicant: Intel Corporation

Inventor： Alexander Krichevsky ,  Boping Xie ,  Sunil Priyadarshi ,  Chao Tian ,  Guojiang Hu ,  Hari Mahalingam ,  Haijiang Yu

IPC: G02B6/42

CPC classification number: G02B6/4206 ,  G02B6/42 ,  G02B6/4214

Abstract: Method and apparatus for vision assisted optical alignment. In the apparatus, one or more main waveguides of a photonic integrated circuit (PIC) are selected, and respective one or more corresponding auxiliary waveguides are terminated with a respective scattering structure. The scattering structures deflect externally supplied light out of the PIC for detection by a camera or photo detector to provide feedback on the amount of light coupled into the main waveguides during the optical alignment process. The method and apparatus eliminate the need to power up the PIC circuitry, speed up the subsequent alignment process, and allow control and failure analysis of multiple channels at once.

公开(公告)号：US12133357B2

公开(公告)日：2024-10-29

申请号：US17123760

申请日：2020-12-16

Applicant: Intel Corporation

Inventor： Jin Yang ,  David Shia ,  Mohanraj Prabhugoud ,  Olaotan Elenitoba-Johnson ,  Craig Jahne ,  Phil Geng

IPC: H05K7/20

CPC classification number: H05K7/20254 ,  H05K7/20418 ,  H05K7/20509

Abstract: Examples described herein relate to a cold plate. In some examples, the cold plate includes a surface with fins and at least two channels, wherein a first channel is shaped with a first opening extending towards the surface, a second opening proximate and across a first fin attached to the surface, and a third opening from the surface and extending away from the surface. In some examples, when a fluid is provided to the first opening, the first opening directs the fluid towards the surface, the second opening directs the fluid across the first fin, and the third opening directs the fluid away from the surface. In some examples, the second opening comprises split openings around opposite sides of the first fin.