公开(公告)号：US12126068B2

公开(公告)日：2024-10-22

申请号：US16912027

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Diego Correas-Serrano ,  Georgios Dogiamis ,  Henning Braunisch ,  Neelam Prabhu Gaunkar ,  Telesphor Kamgaing

IPC: H01P3/16

CPC classification number: H01P3/16

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

公开(公告)号：US12125212B2

公开(公告)日：2024-10-22

申请号：US17132810

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Anthony Rhodes ,  Ke Ding ,  Manan Goel

IPC: G06T7/12 ,  G06T7/33 ,  G06V10/44 ,  G06V10/764

CPC classification number: G06T7/12 ,  G06T7/33 ,  G06V10/454 ,  G06V10/764 ,  G06T2207/20084

Abstract: Methods, systems, and apparatus for high-fidelity vision tasks using deep neural networks are disclosed. An example apparatus includes a feature extractor to extract low-level features and edge-enhanced features of an input image processed using a convolutional neural network, an eidetic memory block generator to generate an eidetic memory block using the extracted low-level features or the extracted edge-enhanced features, and an interactive segmentation network to perform image segmentation using the eidetic memory block, the eidetic memory block used to propagate domain-persistent features through the segmentation network.

公开(公告)号：US12124856B2

公开(公告)日：2024-10-22

申请号：US17211549

申请日：2021-03-24

Applicant: Intel Corporation

Inventor： Subrata Banik ,  Aamir Bohra ,  Vincent Zimmer ,  Robert E. Gough ,  Xiang Ma ,  Jabeena Begum Gaibusab

IPC: G06F9/4401 ,  G06F8/65 ,  G06F15/78 ,  G06F21/57

CPC classification number: G06F9/4411 ,  G06F15/7807 ,  G06F8/65 ,  G06F9/4401 ,  G06F21/572

Abstract: During a computing system boot sequence, reference firmware provided by a computing system component supplies Advanced Configuration and Power Interface (ACPI) code that generates ACPI tables and definition blocks to a bootloader. During a boot sequence, the reference firmware receives an indication from the bootloader which components the reference firmware is to initialize. As part of component initialization performed by the reference firmware, the reference firmware populates hand-off data structures (e.g., hand-off blocks (HOBs)) with ACPI code (AML code) that, when executed by the bootloader, generates and populates ACPI tables (e.g., DSDT and SSDT tables) and definition blocks with information pertinent to the initialization and runtime management of computing system components. Component initialization and runtime configuration workarounds can be implemented in the bootloader incorporating reference firmware updates provided by the component vendor.

公开(公告)号：US12124533B2

公开(公告)日：2024-10-22

申请号：US17482875

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Anbang Yao ,  Ming Lu ,  Yikai Wang ,  Scott Janus ,  Sungye Kim

IPC: G06F18/2136 ,  G06T11/00

CPC classification number: G06F18/2136 ,  G06T11/00 ,  G06T2207/20076 ,  G06T2207/20081

Abstract: Embodiments are generally directed to methods and apparatuses of spatially sparse convolution module for visual rendering and synthesis. An embodiment of a method for image processing, comprising: receiving an input image by a convolution layer of a neural network to generate a plurality of feature maps; performing spatially sparse convolution on the plurality of feature maps to generate spatially sparse feature maps; and upsampling the spatially sparse feature maps to generate an output image.

公开(公告)号：US12124383B2

公开(公告)日：2024-10-22

申请号：US17862739

申请日：2022-07-12

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek Appu ,  Aravindh Anantaraman ,  Valentin Andrei ,  Durgaprasad Bilagi ,  Varghese George ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Pattabhiraman K ,  SungYe Kim ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Xinmin Tian

IPC: G06F12/00 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/123 ,  G06T1/60

CPC classification number: G06F12/123 ,  G06F12/0875 ,  G06F12/0891 ,  G06T1/60 ,  G06F2212/302

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

公开(公告)号：US20240349082A1

公开(公告)日：2024-10-17

申请号：US18552641

申请日：2022-04-29

Applicant: INTEL CORPORATION

Inventor： Ziyi LI ,  Dawei YING ,  Qian LI ,  Zongrui DING

IPC: H04W24/02 ,  H04W60/04

CPC classification number: H04W24/02 ,  H04W60/04

Abstract: This disclosure describes systems, methods, and devices related to collaboration between user equipment (UE) and network for machine learning. A radio access network (RAN) node B device may transmit, to the CE device, an indication that the node B device supports machine learning; identify a service registration, received from the UE device, indicating that the UE device requests machine learning support from the node B device; transmit, to the UE device, a request for information associated with the UE device, the information associated with at least one of hardware capabilities or machine learning capabilities of the UE device; identify the information received from the UE based on the request for information; and transmit, to the UE device, a machine learning configuration for use by the UE device, wherein the machine learning configuration is based on the information.

公开(公告)号：US20240348562A1

公开(公告)日：2024-10-17

申请号：US18757825

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Yotam Nizri ,  Wing Cheung ,  Thang Quang Nguyen ,  Kenneth Keels ,  Noam Elati

IPC: H04L49/00 ,  H04L49/9005

CPC classification number: H04L49/3063 ,  H04L49/9005 ,  H04L49/70

Abstract: A shared networking pipeline is implemented by a network interface device and shared by a plurality of host devices. A pool of shared buffers of a network interface device correspond to one or more stages in the pipeline and are configured to allocate entries to the plurality of host devices based on the respective shares of the shared packet processing pipeline. Data is buffered associated with traffic of a first one of the plurality of host devices in a first subset of shared buffers, where the traffic is to proceed from a first stage to a second stage in the shared packet processing pipeline, and the data is associated with processing of the traffic by the second stage. Forward progress of the traffic is to be prevented from the first stage to the second stage when the first subset of entries are occupied.

公开(公告)号：US20240346979A1

公开(公告)日：2024-10-17

申请号：US18736208

申请日：2024-06-06

Applicant: Intel Corporation

Inventor： Atsuo Kuwahara ,  Deepak S. Vembar ,  Paul S. Diefenbaugh ,  Vallabhajosyula S. Somayazulu ,  Kofi C. Whitney

IPC: G09G3/20 ,  G06F3/01 ,  G06F3/147

CPC classification number: G09G3/2096 ,  G06F3/012 ,  G06F3/147 ,  G09G2320/0252 ,  G09G2320/0261 ,  G09G2320/028 ,  G09G2320/106 ,  G09G2354/00 ,  G09G2360/12 ,  G09G2370/022 ,  G09G2370/16

Abstract: In one example, a head mounted display system includes at least one memory; and at least one processor to execute instructions to: detect a first position and a first view direction of a head of a user based on sensor data generated by at least one of an accelerometer, at least one camera, or a gyroscope at a first point in time; determine a latency associated with a time to cause an image to be presented on the display; determine a predicted position and a predicted view direction of the head of the user at a second point in time based on the latency; render, prior to the second point in time, the image for presentation on the display based on the predicted position and the predicted view direction of the head of the user; and cause the display to present the rendered image.

公开(公告)号：US20240345841A1

公开(公告)日：2024-10-17

申请号：US18751604

申请日：2024-06-24

Applicant: Intel Corporation

Inventor： UTKARSH Y. KAKAIYA ,  RAJESH SANKARAN ,  GILBERT NEIGER ,  PHILIP LANTZ ,  SANJAY K. KUMAR

IPC: G06F9/34 ,  G06F9/30 ,  G06F12/109

CPC classification number: G06F9/34 ,  G06F9/30098 ,  G06F12/109 ,  G06F2212/657

Abstract: In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

公开(公告)号：US20240345639A1

公开(公告)日：2024-10-17

申请号：US18755226

申请日：2024-06-26

Applicant: Intel Corporation

Inventor： Andres Ramirez Macias ,  Aardra B. Athalye ,  Devdatta Prakash Kulkarni ,  Gilberto Rayas Paredes ,  Bijoyraj Sahu

IPC: G06F1/20 ,  H05K1/02

CPC classification number: G06F1/206 ,  H05K1/0272 ,  G06F2200/201

Abstract: Flexible and modular top and bottom side processor unit module cooling is disclosed. An example apparatus comprises a printed circuit board including an integrated circuit component on a first side of the printed circuit board, and an electronic component on a second side of the printed circuit board, the second side facing away from the first side; a stiffener to at least partially enclose the printed circuit board, and a flexible strap to thermally couple the electronic component and a portion of the stiffener, the portion of the stiffener positioned adjacent the first side of the printed circuit board.