公开(公告)号：US20210373975A1

公开(公告)日：2021-12-02

申请号：US17029935

申请日：2020-09-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexandru DUTU ,  Matthew David SINCLAIR ,  Bradford BECKMANN ,  David A. WOOD

IPC: G06F9/52 ,  G06N20/00 ,  G06F11/30 ,  G06F11/34 ,  G06F9/46 ,  G06F9/30

Abstract: A processing system monitors and synchronizes parallel execution of workgroups (WGs). One or more of the WGs perform (e.g., periodically or in response to a trigger such as an indication of oversubscription) a waiting atomic instruction. In response to a comparison between an atomic value produced as a result of the waiting atomic instruction and an expected value, WGs that fail to produce a correct atomic value are identified as being in a waiting state (e.g., waiting for a synchronization variable). Execution of WGs in the waiting state is prevented (e.g., by a context switch) until corresponding synchronization variables are released.

公开(公告)号：US20210373957A1

公开(公告)日：2021-12-02

申请号：US16888540

申请日：2020-05-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Steven J. Tovey ,  Zhuo Chen ,  David Ronald Oldcorn

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/52

Abstract: Techniques for scheduling operations for a task graph on a processing device are provided. The techniques include receiving a task graph that specifies one or more passes, one or more resources, and one or more directed edges between passes and resources; identifying independent passes and dependent passes of the task graph; based on performance criteria of the processing device, scheduling commands to execute the passes; and transmitting scheduled commands to the processing device for execution as scheduled.

公开(公告)号：US20210373892A1

公开(公告)日：2021-12-02

申请号：US16888521

申请日：2020-05-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Steven J. Tovey ,  Zhuo Chen ,  David Ronald Oldcorn

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: Techniques for generating a task graph for workload scheduling based on a task graph specification program are provided. The techniques include executing control flow instructions of the task graph specification program to traverse the task graph specification program; generating pass nodes of the task graph based on pass instructions of the task graph specification program; generating resource nodes and directed edges based on resource declarations of the task graph specification program; and outputting the task graph specification program to a command scheduler for scheduling.

公开(公告)号：US20210358540A1

公开(公告)日：2021-11-18

申请号：US16875281

申请日：2020-05-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

IPC: G11C11/406

Abstract: A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.

公开(公告)号：USRE48819E1

公开(公告)日：2021-11-16

申请号：US16028942

申请日：2018-07-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Morrie Altmejd ,  Evandro Menezes ,  Dave Tobias

IPC: G06F1/32 ,  G06F1/26 ,  G06F1/329 ,  G06F1/3203 ,  G06F1/3228

Abstract: An integrated circuit includes a plurality of functional blocks. Utilization information for the various functional blocks is generated. Based on that information, the power consumption and thus the performance levels of the functional blocks can be tuned. Thus, when a functional block is heavily loaded by an application, the performance level and thus power consumption of that particular functional block is increased. At the same time, other functional blocks that are not being heavily utilized and thus have lower performance requirements can be kept at a relatively low power consumption level. Thus, power consumption can be reduced overall without unduly impacting performance.

公开(公告)号：US11176986B2

公开(公告)日：2021-11-16

申请号：US16730086

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Naveen Davanam ,  Oswin E. Housty

IPC: G11C7/00 ,  G11C11/406 ,  G06F12/02 ,  G06F13/40 ,  G06F13/16 ,  G06F1/3234

Abstract: Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.

公开(公告)号：US20210342285A1

公开(公告)日：2021-11-04

申请号：US16863149

申请日：2020-04-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SeyedMohammad SEYEDZADEHDELCHEH ,  Steven RAASCH ,  Sergey BLAGODUROV

IPC: G06F13/40 ,  H03M7/30 ,  G06F13/42

Abstract: Data are serially communicated over an interconnect between an encoder and a decoder. The encoder includes a first training unit to count a frequency of symbol values in symbol blocks of a set of N number of symbol blocks in an epoch. A circular shift unit of the encoder stores a set of most-recently-used (MRU) amplitude values. An XOR unit is coupled to the first training unit and the first circular shift unit as inputs and to the interconnect as output. A transmitter is coupled to the encoder XOR unit and the interconnect and thereby contemporaneously sends symbols and trains on the symbols. In a system, a device includes a receiver and decoder that receive, from the encoder, symbols over the interconnect. The decoder includes its own training unit for decoding the transmitted symbols.

公开(公告)号：US11158106B2

公开(公告)日：2021-10-26

申请号：US16723969

申请日：2019-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Vineet Goel ,  Pazhani Pillai ,  Ruijin Wu ,  Christopher J. Brennan ,  Andrew S. Pomianowski

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data, and writing a VRS rate feedback buffer based on the updated VRS data.

公开(公告)号：US20210326063A1

公开(公告)日：2021-10-21

申请号：US16848920

申请日：2020-04-15

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ANIRBAN NAG ,  NUWAN JAYASENA ,  SHAIZEEN AGA

IPC: G06F3/06 ,  G06F9/448 ,  G06F9/48

Abstract: Memory operations using compound memory commands, including: receiving, by a memory module, a compound memory command indicating one or more operations to be applied to each portion of a plurality of portions of contiguous memory in the memory module; generating, based on the compound memory command, a plurality of memory commands to apply the one or more operations to each portion of the plurality of portions of contiguous memory; and executing the plurality of memory commands.

公开(公告)号：US11151075B2

公开(公告)日：2021-10-19

申请号：US16221181

申请日：2018-12-14

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gordon Caruk ,  Gerald R. Talbot

IPC: G06F13/42 ,  G06F13/12 ,  G06F13/40

Abstract: An interconnect controller includes a data link layer controller coupled to a transaction layer, wherein the data link layer controller selectively receives data packets from and sends data packets to the transaction layer, and a physical layer controller coupled to the data link layer controller and to a communication link. The physical layer controller selectively operates at a first predetermined link speed. The physical layer controller has an enhanced speed mode, wherein in response to performing a link initialization, the interconnect controller queries a data processing platform to determine whether the enhanced speed mode is permitted, performs at least one setup operation to select an enhanced speed, wherein the enhanced speed is greater than the first predetermined link speed, and subsequently operates the communication link using the enhanced speed.