公开(公告)号：US11531550B2

公开(公告)日：2022-12-20

申请号：US17173067

申请日：2021-02-10

Applicant: Cadence Design Systems, Inc.

Inventor： Robert T. Golla ,  Christopher Olson

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48

Abstract: Techniques are disclosed relating to an apparatus that includes a plurality of execution pipelines including first and second execution pipelines, a shared circuit that is shared by the first and second execution pipelines, and a decode circuit. The first and second execution pipelines are configured to concurrently perform operations for respective instructions. The decode circuit is configured to assign a first program thread to the first execution pipeline and a second program thread to the second execution pipeline. In response to determining that respective instructions from the first and second program threads that utilize the shared circuit are concurrently available for dispatch, the decode circuit is further configured to select between the first program thread and the second program thread.

公开(公告)号：US11520964B1

公开(公告)日：2022-12-06

申请号：US17336315

申请日：2021-06-02

Applicant: Cadence Design Systems, Inc.

Inventor： Ahmad S. Abo Foul ,  Lars Lundgren ,  Björn Håkan Hjort ,  Habeeb Farah ,  Eran Talmor ,  Paula S. Mathias

IPC: G06F30/3323 ,  H04L9/06

Abstract: A method for assertion-based formal verification includes executing a plurality of formal verification regression runs on a model of an electronic design; for each of the regression runs, using a unique signature function, calculating and saving a unique signature value for each instantiation of a property of a plurality of properties of the model of the electronic design and a status result for that instantiation of the property in that regression run; and signing off a current version of the model of the electronic device and presenting as a status result for each the instantiations of a plurality of the properties of the current version of the model of the electronic design the preferred status result obtained for that instantiation of the property per the same unique signature value that was calculated for that instantiation of the property in previous runs of the plurality of formal verification regression runs.

公开(公告)号：US11514222B1

公开(公告)日：2022-11-29

申请号：US17207266

申请日：2021-03-19

Applicant: Cadence Design Systems, Inc.

Inventor： Sheng-En David Lin ,  Yi-Xiao Ding ,  Jhih-Rong Gao ,  Zhuo Li

IPC: G06F30/394 ,  G06F111/04 ,  G06F117/10

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a routing topology for a net comprising interconnections between a set of pins. The IC design further comprises a set of candidate locations for inserting buffers. A set of cells from a cell library in memory is accessed. A candidate location from the set of candidate locations is assessed to determine whether at least one cell in the set of cells fits at the location. Based on determining that at least one cell in the set of cells fits at the candidate location, the location is marked as bufferable. A largest cell width that fits at the candidate location is determined based on the set of cells and a buffering solution is generated for the net using the largest cell width as a constraint on buffer insertion performed at the candidate location.

公开(公告)号：US11513818B1

公开(公告)日：2022-11-29

申请号：US16948771

申请日：2020-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Rong Chen ,  He Xiao ,  Nenad Nedeljkovic ,  Nupur B. Andrews ,  Dan Nicolaescu ,  James Sangkyu Kim

IPC: G06F9/445 ,  G06F8/41

Abstract: An approach includes the use of a description of instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions. In some embodiments, the instructions for invoking hardware accelerator and for a hardware accelerator to execute those instructions are described using a single language. These descriptions are then compiled into other languages for use in tool chains for generating simulators (a hardware and instruction set simulator and a hardware accelerator simulator). In some embodiments, the approach illustrated herein can be combined with state machine functionality to manage the execution of instructions that require multiple states. In some embodiments, the approach illustrated herein can be combined with an external register file for transferring information between a processor and a hardware accelerator.

公开(公告)号：US11483185B1

公开(公告)日：2022-10-25

申请号：US17246581

申请日：2021-04-30

Applicant: Cadence Design Systems, Inc.

Inventor： Sachin Ramesh Gugwad ,  Hari Anand Ravi ,  Aaron Willey ,  Thomas E. Wilson

IPC: H04L25/03

Abstract: Disclosed is an improved approach for a training approach to implement DFE for an electronic circuit. The inventive concept is particularity suitable to address, for example, circuits that implement high speed parallel data transmission protocols, such as GDDR6, that are used for graphics applications. The training scheme uses minimal hardware when compared to existing schemes by reusing calibration receiver in auto zeroing receiver as error receiver. Further it works for closed eyes by running the algorithm multiple times with gradual increase in complexity of training pattern, where DFE coefficients from previous iteration is used for the current iteration, thereby gradually opening the eye.

公开(公告)号：US11474844B1

公开(公告)日：2022-10-18

申请号：US17247927

申请日：2020-12-30

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Mitchell G. Poplack ,  Justin Schmelzer

IPC: G06F9/445 ,  G06F9/455

Abstract: Embodiments described herein include an emulator system having a synchronization subsystem comprising devices, organized in logical hierarchy, controlling synchronization of a system clock and system components during emulation execution. The devices of the logical hierarchy communicate bi-directionally, communicating status indicators upwards and execution instructions downwards. A TCI is designated “master TCI” and others are designated “slave TCIs.” The master TCI asserts a RDY status that propagates upwards to a root node for a number cycles. The slave TCIs execute in “infinite run” and continually assert the RDY status upwards to the root device regardless of the cycle count. The root node detects each RDY status and propagates downwards a GO instruction to the master TCI and the slave TCIs. In this way, the TCIs execute until the master TCI de-asserts RDY status. The result is only the master TCI is manipulated to, for example, start/stop emulation or perform iterative execution.

公开(公告)号：US11467620B1

公开(公告)日：2022-10-11

申请号：US16217503

申请日：2018-12-12

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Yuhei Hayashi ,  Mitchell G. Poplack

IPC: G06F1/08 ,  G06F13/42 ,  G06N20/00 ,  G06F13/40

Abstract: Embodiments disclosed herein describe systems and methods for tuning phases of interface clocks of ASICs in an emulation system for a low latency channel and to avoid read errors. During a bring-up time (e.g., powering up) of the emulation system, one or more training processors may execute a software application to iteratively tune the phases of the interface clocks such that data is written to the interface buffers prior to being read out. To mitigate the problem of higher latency, the training processors may execute software application to tune the clock phases such that there is a small time lag between the writes and reads. The training processors may set the time lag to account for factors such as memory setup and hold, clock skews, clock jitters, and the predicted margin required to account for future clock drift due to carrying operating conditions.

公开(公告)号：US11463284B1

公开(公告)日：2022-10-04

申请号：US17305572

申请日：2021-07-09

Applicant: Cadence Design Systems, Inc.

Inventor： Mathieu Gagnon

IPC: H04L25/03

Abstract: Various embodiments described herein provide for a receiver device that includes a processor, a non-linear equalizer, an accumulation register, and a plurality of co-processors. Each of the plurality of co-processors is operably coupled to the processor, the non-linear equalizer, and the accumulation register. Each of the plurality of co-processors can be configured to receive a configuration value from the processor, receive a data signal for processing from the non-linear equalizer, process the data signal based on the configuration value, and provide at least a portion of the processed data signal to the processor.

公开(公告)号：US11449654B1

公开(公告)日：2022-09-20

申请号：US17146019

申请日：2021-01-11

Applicant: Cadence Design Systems, Inc.

Inventor： Nicholas Claude Warren ,  Matthew Noseworthy ,  Liam Cadigan ,  Darryl Frank Day ,  Mihir Milan Shah

IPC: G06F30/31 ,  G06F111/02 ,  G06F115/12 ,  G06F111/18

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, at a client electronic device, an image of an electronic circuit and storing an electronic circuit design file. Embodiments may further include identifying the electronic circuit design file based upon, at least in part, the image of the electronic circuit. Embodiments may also include displaying a graphical representation of the electronic circuit at a display screen associated with the client electronic device.

公开(公告)号：US11436402B1

公开(公告)日：2022-09-06

申请号：US17219695

申请日：2021-03-31

Applicant: Cadence Design Systems, Inc.

Inventor： Miao Liu ,  Liqun Deng ,  Guozhi Xu

IPC: G06F30/392 ,  G06F30/31 ,  G06F119/12

Abstract: Disclosed is an improved approach for implementing a three-dimensional integrated circuit design with mixed macro and standard cell placement. This approach concurrently places both the macros and standard cells of the 3D-IC design onto two or more stacked floorplan and optimize the instance locations by timing, density, wire length and floorplan constraint.