公开(公告)号：US20130265820A1

公开(公告)日：2013-10-10

申请号：US13443056

申请日：2012-04-10

Applicant: Yue-Der CHIH ,  Chin- Yi HUANG ,  Chun-Jung LIN ,  Kai-Chun LIN ,  Hung-Chang YU

Inventor： Yue-Der CHIH ,  Chin- Yi HUANG ,  Chun-Jung LIN ,  Kai-Chun LIN ,  Hung-Chang YU

IPC: G11C11/16

CPC classification number: G11C11/16 ,  G11C11/15 ,  G11C11/1673

Abstract: Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position.

Abstract translation: 阵列中的磁阻存储器位单元具有存储逻辑值的高或低电阻状态。 在读取操作期间，偏置源耦合到寻址的存储器字，将与单元电阻相关的参数耦合到每个位位置的读出放大器。 读出放大器确定参数值是大于还是小于高电阻状态和低电阻状态之间的参考值。 参考值是通过在高和/或低电阻状态下对参考电池的电阻差进行平均或分割得出的。 由于感测放大器和寻址的存储器字之间的距离不同，偏置电流在具有变化的电阻的地址线上进行，这通过将来自虚拟寻址阵列的电阻插入到比较电路中来抵消，等于导体寻址的电阻 选择的字线和位位置。

公开(公告)号：US08541877B2

公开(公告)日：2013-09-24

申请号：US12849089

申请日：2010-08-03

Applicant: Chia-Lun Tsai ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

Inventor： Chia-Lun Tsai ,  Ching-Yu Ni ,  Tien-Hao Huang ,  Chia-Ming Cheng ,  Wen-Cheng Chien ,  Nan-Chun Lin ,  Wei-Ming Chen ,  Shu-Ming Chang ,  Bai-Yao Lou

IPC: H01L23/48

CPC classification number: H01L24/20 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.

Abstract translation: 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上，电连接到导电焊盘。

公开(公告)号：US08536881B2

公开(公告)日：2013-09-17

申请号：US12895871

申请日：2010-10-01

Applicant: Ching-Chun Lin ,  Wing-Kai Tang ,  Ching-Ho Hung ,  Tsen-Wei Chang ,  Yi-Liang Lin ,  Jiun-Jie Tsai

Inventor： Ching-Chun Lin ,  Wing-Kai Tang ,  Ching-Ho Hung ,  Tsen-Wei Chang ,  Yi-Liang Lin ,  Jiun-Jie Tsai

IPC: G01R27/26

CPC classification number: G06F3/044

Abstract: A touch sensing system which includes a touch input interface and a capacitance sensing circuit is provided. The touch input interface includes a plurality of sensing capacitors which output at least one waveform under test and at least one reference waveform. The capacitance sensing circuit includes a difference comparing unit. The difference comparing unit receives the waveform under test and the reference waveform and outputs a differential signal according to at least one positive edge difference and at least one negative edge difference between the waveform under test and the reference waveform. Furthermore, a capacitance sensing method is also provided.

Abstract translation: 提供一种包括触摸输入接口和电容感测电路的触摸感测系统。 触摸输入接口包括多个感测电容器，其输出至少一个待测波形和至少一个参考波形。 电容感测电路包括差分比较单元。 差分比较单元接收待测波形和参考波形，并根据被测波形与参考波形之间的至少一个正沿差和至少一个负沿差输出差分信号。 此外，还提供了电容感测方法。

公开(公告)号：US08525336B2

公开(公告)日：2013-09-03

申请号：US13349049

申请日：2012-01-12

Applicant: Pang-Chun Lin ,  Yueh-Ying Tsai ,  Yong-Liang Chen

Inventor： Pang-Chun Lin ,  Yueh-Ying Tsai ,  Yong-Liang Chen

IPC: H01L23/48 ,  H01L29/40

CPC classification number: H01L21/4846 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2924/014

Abstract: This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased.

Abstract translation: 本公开提供了一种半导体封装及其制造方法。 半导体封装包括绝缘层; 布置在绝缘层中并从绝缘层突出的多个迹线和连接焊盘; 形成在多个迹线上的多个凸块; 设置在所述凸块上的半导体芯片; 以及形成在所述绝缘层上以封装所述半导体芯片，所述多个凸块，迹线和连接焊盘的密封剂。 当形成密封剂时，可以防止在迹线和连接焊盘中产生空隙，从而显着增加工艺的产量。

公开(公告)号：US08517046B2

公开(公告)日：2013-08-27

申请号：US12617143

申请日：2009-11-12

Applicant: Chun Lin ,  Roy Ronald Pelfrey ,  Eric Alan Miller

Inventor： Chun Lin ,  Roy Ronald Pelfrey ,  Eric Alan Miller

IPC: F16K43/00

CPC classification number: F16K1/385 ,  F16K25/00 ,  F16K31/52408 ,  F16K39/024 ,  Y10T137/6167 ,  Y10T137/7868 ,  Y10T137/86944 ,  Y10T137/87394

Abstract: Redundant metal-to-metal seals for use with internal valves are described. A plug having redundant sealing functionality for use with a poppet of an internal valve includes a tapered surface to sealingly engage a seat of the poppet. Additionally, the plug includes a seal adjacent the tapered surface and disposed in a groove defined by the plug to sealingly engage the seat.

Abstract translation: 描述了用于内部阀门的冗余金属对金属密封件。 具有用于与内部阀的提升阀一起使用的冗余密封功能的插头包括锥形表面，以密封地接合提升阀座。 此外，插头包括邻近锥形表面的密封件，并且设置在由插头限定的凹槽中以密封地接合座椅。

公开(公告)号：US20130207187A1

公开(公告)日：2013-08-15

申请号：US13372037

申请日：2012-02-13

Applicant: Ker Hsiao HUO ,  Chih-Chang CHENG ,  Ru-Yi SU ,  Jen-Hao YEH ,  Fu-Chih YANG ,  Chun Lin TSAI

Inventor： Ker Hsiao HUO ,  Chih-Chang CHENG ,  Ru-Yi SU ,  Jen-Hao YEH ,  Fu-Chih YANG ,  Chun Lin TSAI

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7394 ,  H01L21/26533 ,  H01L21/76243 ,  H01L21/76283 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66325 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7824 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Abstract translation: 在本公开中提供了高电压金属氧化物半导体横向扩散器件（HV LDMOS），特别是绝缘栅双极结型晶体管（IGBT）及其制造方法。 该器件包括半导体衬底，形成在衬底上的栅极结构，在栅极结构的任一侧上的衬底中形成的源极和漏极，在衬底中形成的第一掺杂阱和形成在第一衬底中的第二掺杂阱 好。 栅极，源极，第二掺杂阱，第一阱的一部分和漏极结构的一部分被硅衬底中的深沟槽隔离特征和注入的氧层包围。

公开(公告)号：US20130200490A1

公开(公告)日：2013-08-08

申请号：US13367064

申请日：2012-02-06

Applicant: Tai-Chun Lin ,  Wen-Tsao Chen ,  Chih-Ho Tai ,  Ming-Ray Mao ,  Kuan-Chi Tsai

Inventor： Tai-Chun Lin ,  Wen-Tsao Chen ,  Chih-Ho Tai ,  Ming-Ray Mao ,  Kuan-Chi Tsai

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/3105

Abstract: Disclosed embodiments include a capacitor structure and a method for forming a capacitor structure. An embodiment is a structure comprising a conductor-insulator-conductor capacitor on a substrate. The conductor-insulator-conductor capacitor comprises a first conductor on the substrate, a dielectric stack over the first conductor, and a second conductor over the dielectric stack. The dielectric stack comprises a first nitride layer, a first oxide layer over the first nitride layer, and a second nitride layer over the first oxide layer. A further embodiment is a method comprising forming a first conductor on a substrate; forming a first nitride layer over the first conductor; treating the first nitride layer with a first nitrous oxide (N2O) treatment to form an oxide layer on the first nitride layer; forming a second nitride layer over the oxide layer; and forming a second conductor over the second nitride layer.

Abstract translation: 公开的实施例包括电容器结构和形成电容器结构的方法。 实施例是在基板上包括导体 - 绝缘体 - 导体电容器的结构。 导体 - 绝缘体 - 导体电容器包括在基板上的第一导体，在第一导体上的电介质堆叠，以及位于介电叠层上的第二导体。 电介质堆叠包括第一氮化物层，第一氮化物层上的第一氧化物层和第一氧化物层上的第二氮化物层。 另一实施例是一种方法，包括在衬底上形成第一导体; 在所述第一导体上形成第一氮化物层; 用第一氧化亚氮（N2O）处理第一氮化物层以在第一氮化物层上形成氧化物层; 在所述氧化物层上形成第二氮化物层; 以及在所述第二氮化物层上形成第二导体。

公开(公告)号：US20130188418A1

公开(公告)日：2013-07-25

申请号：US13356920

申请日：2012-01-24

Applicant: Tien-Wei CHIANG ,  Kai-Chun LIN ,  Ya-Chen KAO ,  Hung-Chang YU

Inventor： Tien-Wei CHIANG ,  Kai-Chun LIN ,  Ya-Chen KAO ,  Hung-Chang YU

IPC: G11C11/16 ,  H01L29/82

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08

Abstract: A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed above or below the MTJ. The induction line is configured to induce a magnetic field at the MTJ.

Abstract translation: 磁阻随机存取存储器（MRAM）单元包括磁性隧道结（MTJ），设置在MTJ上方的顶部电极，设置在MTJ下方的底部电极以及设置在MTJ上方或下方的感应线。 感应线被配置为在MTJ处诱导磁场。

公开(公告)号：US08487890B2

公开(公告)日：2013-07-16

申请号：US12705232

申请日：2010-02-12

Applicant: Yi Chung Juan ,  Chia Hua Yu ,  Sung Chun Lin ,  Hsu Ho Wu

Inventor： Yi Chung Juan ,  Chia Hua Yu ,  Sung Chun Lin ,  Hsu Ho Wu

IPC: G06F3/041

CPC classification number: G06F3/0412 ,  G06F3/045

Abstract: An in-cell touch-sensitive panel includes TFT and CF substrates. The TFT substrate includes a net-shaped readout circuit and conductive pads arranged in array manner. The net-shaped readout circuit includes widthwise and lengthwise readout lines. The widthwise readout lines are electrically connected to the lengthwise readout lines. The conductive pads are electrically connected to the net-shaped readout circuit. Spacers are adapted to keep a first gap between the TFT and CF substrates. Protrudent portions are arranged to be corresponding to the conductive pads, and there is a second gap between the protrudent portion and the conductive pad. A transparent electrode covers the spacers and the protrudent portion.

Abstract translation: 单元内触摸屏包括TFT和CF基板。 TFT基板包括网状读​​出电路和以阵列方式布置的导电焊盘。 网状读出电路包括宽度方向和长度方向的读出线。 横向读出线电连接到纵向读出线。 导电焊盘电连接到网状读出电路。 隔板适于保持TFT和CF基板之间的第一间隙。 突出部分被布置成对应于导电焊盘，并且在突出部分和导电焊盘之间存在第二间隙。 透明电极覆盖间隔物和凸起部分。

公开(公告)号：US20130154961A1

公开(公告)日：2013-06-20

申请号：US13488462

申请日：2012-06-05

Applicant: Hsu-Ho Wu ,  Sung-Chun Lin ,  Hsuan-Chen Liu ,  Yi-Chung Juan

Inventor： Hsu-Ho Wu ,  Sung-Chun Lin ,  Hsuan-Chen Liu ,  Yi-Chung Juan

IPC: G06F3/041

CPC classification number: G06F3/041 ,  G06F2203/04107

Abstract: A touch panel and a touch display device are disclosed, in which the touch panel includes a substrate, a touch component layer and a shielding-electrode film. The substrate has a surface. The touch component layer is disposed on the surface of the substrate and includes a metallic layer, an electrode layer, a protection layer and a hard coat layer. The protection layer is disposed between the metallic layer and the electrode layer. The hard coat layer at least covers the metallic layer and the electrode layer. The shielding-electrode film is disposed on the hard coat layer of the touch component layer, wherein the touch component layer is located between the substrate and the shielding-electrode film, and a resistance of the shielding-electrode film is greater than a resistance of the electrode layer.

Abstract translation: 公开了触摸面板和触摸显示装置，其中触摸面板包括基板，触摸部件层和屏蔽电极膜。 基板具有表面。 触摸部件层设置在基板的表面上，具有金属层，电极层，保护层和硬涂层。 保护层设置在金属层和电极层之间。 硬涂层至少覆盖金属层和电极层。 屏蔽电极膜设置在触摸部件层的硬涂层上，其中触摸部件层位于基板和屏蔽电极膜之间，屏蔽电极膜的电阻大于 电极层。