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    FABRICATION METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE
    3.
    发明申请
    FABRICATION METHOD OF SEMICONDUCTOR PACKAGE STRUCTURE 有权
    半导体封装结构的制造方法

    公开(公告)号：US20110159643A1

    公开(公告)日：2011-06-30

    申请号：US12770059

    申请日：2010-04-29

    Applicant: Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    Inventor： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    IPC: H01L21/60 ,  H01L21/56

    CPC classification number: H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging.

    Abstract translation: 半导体封装结构的制造方法包括：图案化具有第一表面和第二表面的金属板; 在所述金属板上形成电介质层; 在所述第一表面和所述电介质层上形成金属层; 在所述第二表面上形成金属焊盘，所述金属层具有管芯焊盘并且各自具有接合焊盘; 将半导体芯片安装在芯片焊盘上，然后通过接合线将半导体芯片电连接到焊盘; 形成密封剂以覆盖半导体芯片和金属层; 去除未被金属垫覆盖的金属板的部分，以形成金属柱; 并执行单独处理。 该制造方法的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免焊料桥接。

    Packaging substrate and fabrication method thereof
    6.
    发明授权
    Packaging substrate and fabrication method thereof 有权
    包装基板及其制造方法

    公开(公告)号：US09171741B2

    公开(公告)日：2015-10-27

    申请号：US13566265

    申请日：2012-08-03

    Applicant: Wei-Ping Wang ,  Pang-Chun Lin ,  Chin-Chih Hsiao ,  Kaun-i Cheng ,  Cheng-Wen Chiu

    Inventor： Wei-Ping Wang ,  Pang-Chun Lin ,  Chin-Chih Hsiao ,  Kaun-i Cheng ,  Cheng-Wen Chiu

    IPC: H01L21/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

    CPC classification number: H01L21/4857 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A method for fabricating a packaging substrate includes: providing a carrier having a first metal layer and a second metal layer formed on the first metal layer; forming a first circuit layer on the second metal layer and forming a separating portion on an edge of the second metal layer such that the separating portion is spaced from the first circuit layer; forming a dielectric layer on the second metal layer and the first circuit layer such that the first circuit layer and the separating portion are embedded in the dielectric layer and portions of the dielectric layer are formed between the first circuit layer and the separating portion; forming a second circuit layer on the dielectric layer; and applying forces on the separating portion so as to remove the first metal layer and the carrier, thereby maintaining the integrity of the first circuit layer.

    Abstract translation: 一种用于制造封装衬底的方法，包括：提供具有形成在第一金属层上的第一金属层和第二金属层的载体; 在所述第二金属层上形成第一电路层，并在所述第二金属层的边缘上形成分离部分，使得所述分离部分与所述第一电路层隔开; 在所述第二金属层和所述第一电路层上形成介电层，使得所述第一电路层和所述分离部分嵌入在所述电介质层中，并且所述电介质层的部分形成在所述第一电路层与所述分离部之间; 在所述电介质层上形成第二电路层; 并且在分离部分上施加力以便去除第一金属层和载体，从而保持第一电路层的完整性。

    Fabrication method of semiconductor package structure
    8.
    发明授权
    Fabrication method of semiconductor package structure 有权
    半导体封装结构的制造方法

    公开(公告)号：US08304268B2

    公开(公告)日：2012-11-06

    申请号：US12770059

    申请日：2010-04-29

    Applicant: Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    Inventor： Pang-Chun Lin ,  Chun-Yuan Li ,  Chien-Ping Huang ,  Chun-Chi Ke

    IPC: H01L21/44

    CPC classification number: H01L23/495 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/4951 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/181 ,  Y10T29/49117 ,  Y10T29/49171 ,  Y10T29/49172 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A fabrication method of a semiconductor package structure includes: patterning a metal plate having first and second surfaces; forming a dielectric layer on the metal plate; forming a metal layer on the first surface and the dielectric layer; forming metal pads on the second surface, the metal layer having a die pad and traces each having a bond pad; mounting a semiconductor chip on the die pad, followed by connecting electrically the semiconductor chip to the bond pads through bonding wires; forming an encapsulant to cover the semiconductor chip and the metal layer; removing portions of the metal plate not covered by the metal pads so as to form metal pillars; and performing a singulation process. The fabrication method is characterized by disposing traces with bond pads close to the die pad to shorten the bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging.

    Abstract translation: 半导体封装结构的制造方法包括：图案化具有第一表面和第二表面的金属板; 在所述金属板上形成电介质层; 在所述第一表面和所述电介质层上形成金属层; 在所述第二表面上形成金属焊盘，所述金属层具有管芯焊盘并且各自具有接合焊盘; 将半导体芯片安装在芯片焊盘上，然后通过接合线将半导体芯片电连接到焊盘; 形成密封剂以覆盖半导体芯片和金属层; 去除未被金属垫覆盖的金属板的部分，以形成金属柱; 并执行单独处理。 该制造方法的特征在于，将具有接合焊盘的迹线设置在芯片焊盘附近以缩短接合线并形成从电介质层突出的金属柱，以避免焊料桥接。

    Semiconductor package and method of fabricating the same
    9.
    发明授权
    Semiconductor package and method of fabricating the same 有权
    半导体封装及其制造方法

    公开(公告)号：US08525336B2

    公开(公告)日：2013-09-03

    申请号：US13349049

    申请日：2012-01-12

    Applicant: Pang-Chun Lin ,  Yueh-Ying Tsai ,  Yong-Liang Chen

    Inventor： Pang-Chun Lin ,  Yueh-Ying Tsai ,  Yong-Liang Chen

    IPC: H01L23/48 ,  H01L29/40

    CPC classification number: H01L21/4846 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2924/014

    Abstract: This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased.

    Abstract translation: 本公开提供了一种半导体封装及其制造方法。 半导体封装包括绝缘层; 布置在绝缘层中并从绝缘层突出的多个迹线和连接焊盘; 形成在多个迹线上的多个凸块; 设置在所述凸块上的半导体芯片; 以及形成在所述绝缘层上以封装所述半导体芯片，所述多个凸块，迹线和连接焊盘的密封剂。 当形成密封剂时，可以防止在迹线和连接焊盘中产生空隙，从而显着增加工艺的产量。

    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 有权
    半导体封装及其制造方法

    公开(公告)号：US20130093086A1

    公开(公告)日：2013-04-18

    申请号：US13349049

    申请日：2012-01-12

    Applicant: Pang-Chun Lin ,  Yueh-Ying Tsai ,  Yong-Liang Chen

    Inventor： Pang-Chun Lin ,  Yueh-Ying Tsai ,  Yong-Liang Chen

    IPC: H01L23/488 ,  H01L21/28

    CPC classification number: H01L21/4846 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2924/014

    Abstract: This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased.

    Abstract translation: 本公开提供了一种半导体封装及其制造方法。 半导体封装包括绝缘层; 布置在绝缘层中并从绝缘层突出的多个迹线和连接焊盘; 形成在多个迹线上的多个凸块; 设置在所述凸块上的半导体芯片; 以及形成在所述绝缘层上以封装所述半导体芯片，所述多个凸块，迹线和连接焊盘的密封剂。 当形成密封剂时，可以防止在迹线和连接焊盘中产生空隙，从而显着增加工艺的产量。

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