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公开(公告)号:US20120161315A1
公开(公告)日:2012-06-28
申请号:US12975698
申请日:2010-12-22
申请人: Nan-Chun Lin , Ya-Yun Cheng
发明人: Nan-Chun Lin , Ya-Yun Cheng
IPC分类号: H01L23/498
CPC分类号: H01L23/5389 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/96 , H01L25/0657 , H01L2223/54433 , H01L2223/54486 , H01L2224/02311 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05548 , H01L2224/05569 , H01L2224/12105 , H01L2224/131 , H01L2224/1403 , H01L2224/16145 , H01L2224/29147 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2224/73267 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2924/01029 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/18162 , H01L2924/19107 , H01L2924/3025 , H01L2924/351 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: The present invention provides a three-dimensional System-In-Package (SIP) Package-On-Package (POP) structure comprising a support element formed around a first electronic device. A filling material is filled between the first electronic device and the support element. Signal channels are coupled to first die pads of the first electronic device. Conductive elements form signal connection between the first end of the signal channels and the second die pads of a second electronic device.
摘要翻译: 本发明提供了一种三维系统级封装(SIP)封装封装(POP)结构,其包括围绕第一电子设备形成的支撑元件。 填充材料填充在第一电子装置和支撑元件之间。 信号通道耦合到第一电子设备的第一裸片焊盘。 导电元件在信号通道的第一端和第二电子设备的第二裸片焊盘之间形成信号连接。
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公开(公告)号:US08619431B2
公开(公告)日:2013-12-31
申请号:US12975698
申请日:2010-12-22
申请人: Nan-Chun Lin , Ya-Yun Cheng
发明人: Nan-Chun Lin , Ya-Yun Cheng
IPC分类号: H05K1/18
CPC分类号: H01L23/5389 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/562 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/96 , H01L25/0657 , H01L2223/54433 , H01L2223/54486 , H01L2224/02311 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/05548 , H01L2224/05569 , H01L2224/12105 , H01L2224/131 , H01L2224/1403 , H01L2224/16145 , H01L2224/29147 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73207 , H01L2224/73265 , H01L2224/73267 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2924/01029 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15321 , H01L2924/181 , H01L2924/18162 , H01L2924/19107 , H01L2924/3025 , H01L2924/351 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要: The present invention provides a three-dimensional System-In-Package (SIP) Package-On-Package (POP) structure comprising a support element formed around a first electronic device. A filling material is filled between the first electronic device and the support element. Signal channels are coupled to first die pads of the first electronic device. Conductive elements form signal connection between the first end of the signal channels and the second die pads of a second electronic device.
摘要翻译: 本发明提供了一种三维系统级封装(SIP)封装封装(POP)结构,其包括围绕第一电子设备形成的支撑元件。 填充材料填充在第一电子装置和支撑元件之间。 信号通道耦合到第一电子设备的第一裸片焊盘。 导电元件在信号通道的第一端和第二电子设备的第二裸片焊盘之间形成信号连接。
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公开(公告)号:US20110140267A1
公开(公告)日:2011-06-16
申请号:US12849089
申请日:2010-08-03
申请人: Chia-Lun TSAI , Ching-Yu Ni , Tien-Hao Huang , Chia-Ming Cheng , Wen-Cheng Chien , Nan-Chun Lin , Wei-Ming Chen , Shu-Ming Chang , Bai-Yao Lou
发明人: Chia-Lun TSAI , Ching-Yu Ni , Tien-Hao Huang , Chia-Ming Cheng , Wen-Cheng Chien , Nan-Chun Lin , Wei-Ming Chen , Shu-Ming Chang , Bai-Yao Lou
IPC分类号: H01L23/498 , H01L21/60
CPC分类号: H01L24/20 , H01L23/13 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L2223/54426 , H01L2223/54473 , H01L2223/54486 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/32225 , H01L2224/73267 , H01L2224/83132 , H01L2224/92 , H01L2224/92244 , H01L2924/01005 , H01L2924/01013 , H01L2924/01021 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15184 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要: The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.
摘要翻译: 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上,电连接到导电焊盘。
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公开(公告)号:US08293572B2
公开(公告)日:2012-10-23
申请号:US13010192
申请日:2011-01-20
申请人: Wen-Chuan Chen , Nan-Chun Lin
发明人: Wen-Chuan Chen , Nan-Chun Lin
IPC分类号: H01L21/00
CPC分类号: H01L21/565 , B29C45/14639 , H01L23/3121 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/00
摘要: The injection molding system comprises a substrate, an inner cover, a molding tool, and a bottom plate. The substrate is used to locate at least one semiconductor device under molding and the inner cover with at least one first injection via, cavity and runner placed over the substrate. In addition, the molding tool includes at least one second injecting via aligned with the runner and the bottom plate is placed under the substrate. Furthermore, a filling material is filled into the cavity and runner of the inner cover during molding. In order to avoid overflowing the filling material, the system further comprises an O-ring placed between the molding tool and the inner cover. The inner radius of the O-ring corresponds with the inner radius of the injection via and is aligned with it.
摘要翻译: 注塑系统包括基底,内盖,模制工具和底板。 衬底用于在模制下定位至少一个半导体器件,并且内盖具有放置在衬底上的至少一个第一注入通孔,空腔和流道。 此外,成型工具包括至少一个与流道对准的第二注射孔,并且底板被放置在基底之下。 此外,在成型期间,将填充材料填充到内盖的空腔和流道中。 为了避免填充材料溢出,系统还包括置于模制工具和内盖之间的O形环。 O形环的内半径对应于注射通孔的内半径并与其对准。
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公开(公告)号:US20120188727A1
公开(公告)日:2012-07-26
申请号:US13011937
申请日:2011-01-24
申请人: Nan-Chun LIN , Ya-Yun Cheng , Jing-Hua Cheng , Kuang-San Liu
发明人: Nan-Chun LIN , Ya-Yun Cheng , Jing-Hua Cheng , Kuang-San Liu
CPC分类号: H05K9/0026 , H01L21/561 , H01L23/26 , H01L23/3135 , H01L23/552 , H01L24/10 , H01L24/16 , H01L24/81 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/81815 , H01L2224/97 , H01L2924/01029 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/19105 , H01L2924/00014 , H01L2224/81 , H01L2924/00
摘要: The present invention discloses a package module with EMI shielding and the method thereof. The package module has a substrate or a PCB with at least one ground pad. A variety of electronic components are mounted on the substrate. The dielectric layer overlays a selected area which covers some electronic components and ground pads. Openings are formed within the dielectric layer and above ground pads. The shielding layer with at least two metal layers covers the dielectric layer and is electrically coupled, via the openings, to the ground pad. In general, there is a protection layer to encapsulate the entire substrate. The package module of the present invention not only achieves the requirement of miniature packaging but also reduces EMI caused by high speed electronic devices.
摘要翻译: 本发明公开了一种具有EMI屏蔽的封装模块及其方法。 封装模块具有至少一个接地焊盘的基板或PCB。 各种电子部件安装在基板上。 电介质层覆盖覆盖一些电子部件和接地焊盘的选定区域。 在电介质层和接地焊盘之上形成开口。 具有至少两个金属层的屏蔽层覆盖电介质层,并且经由开口电耦合到接地垫。 通常,存在用于封装整个基板的保护层。 本发明的封装模块不仅实现了微型封装的要求,而且降低了由高速电子器件引起的EMI。
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公开(公告)号:US20120187582A1
公开(公告)日:2012-07-26
申请号:US13010192
申请日:2011-01-20
申请人: Wen-Chuan Chen , Nan-Chun Lin
发明人: Wen-Chuan Chen , Nan-Chun Lin
CPC分类号: H01L21/565 , B29C45/14639 , H01L23/3121 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2223/6677 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/00
摘要: The injection molding system comprises a substrate, an inner cover, a molding tool, and a bottom plate. The substrate is used to locate at least one semiconductor device under molding and the inner cover with at least one first injection via, cavity and runner placed over the substrate. In addition, the molding tool includes at least one second injecting via aligned with the runner and the bottom plate is placed under the substrate. Furthermore, a filling material is filled into the cavity and runner of the inner cover during molding. In order to avoid overflowing the filling material, the system further comprises an O-ring placed between the molding tool and the inner cover. The inner radius of the O-ring corresponds with the inner radius of the injection via and is aligned with it.
摘要翻译: 注塑系统包括基底,内盖,模制工具和底板。 衬底用于在模制下定位至少一个半导体器件,并且内盖具有放置在衬底上的至少一个第一注入通孔,空腔和流道。 此外,成型工具包括至少一个与流道对准的第二注射孔,并且底板被放置在基底之下。 此外,在成型期间,将填充材料填充到内盖的空腔和流道中。 为了避免填充材料溢出,系统还包括置于模制工具和内盖之间的O形环。 O形环的内半径对应于注射通孔的内半径并与其对准。
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公开(公告)号:US08541877B2
公开(公告)日:2013-09-24
申请号:US12849089
申请日:2010-08-03
申请人: Chia-Lun Tsai , Ching-Yu Ni , Tien-Hao Huang , Chia-Ming Cheng , Wen-Cheng Chien , Nan-Chun Lin , Wei-Ming Chen , Shu-Ming Chang , Bai-Yao Lou
发明人: Chia-Lun Tsai , Ching-Yu Ni , Tien-Hao Huang , Chia-Ming Cheng , Wen-Cheng Chien , Nan-Chun Lin , Wei-Ming Chen , Shu-Ming Chang , Bai-Yao Lou
IPC分类号: H01L23/48
CPC分类号: H01L24/20 , H01L23/13 , H01L23/3121 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L23/544 , H01L24/19 , H01L2223/54426 , H01L2223/54473 , H01L2223/54486 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/32225 , H01L2224/73267 , H01L2224/83132 , H01L2224/92 , H01L2224/92244 , H01L2924/01005 , H01L2924/01013 , H01L2924/01021 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/15184 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要: The invention provides an electronic device package and a method for fabricating the same. The electronic device package includes a carrier wafer. An electronic device chip with a plurality of conductive pads thereon is disposed over the carrier wafer. An isolation laminating layer includes a lower first isolation layer, which covers the carrier wafer and the electronic device chip, and an upper second isolation layer. The isolation laminating layer has a plurality of openings to expose the conductive pads. A plurality of redistribution patterns is conformably formed on the isolation laminating layer and in the openings. The redistribution patterns are electrically connected to the conductive pads, respectively. A plurality of conductive bumps is respectively formed on the redistribution patterns, electrically connected to the conductive pads.
摘要翻译: 本发明提供一种电子器件封装及其制造方法。 电子器件封装包括载体晶片。 具有多个导电焊盘的电子器件芯片设置在载体晶片上。 隔离层压层包括覆盖载体晶片和电子器件芯片的下部第一隔离层和上部第二隔离层。 隔离层压层具有多个开口以露出导电垫。 在隔离层压层和开口中顺应地形成多个再分配图案。 再分布图案分别电连接到导电焊盘。 多个导电凸块分别形成在再分布图案上,电连接到导电焊盘。
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公开(公告)号:US20090227048A1
公开(公告)日:2009-09-10
申请号:US12042093
申请日:2008-03-04
申请人: Li-Chih FANG , Wen-Jeng Fan , Nan-Chun Lin
发明人: Li-Chih FANG , Wen-Jeng Fan , Nan-Chun Lin
IPC分类号: H01L21/66
CPC分类号: H01L21/67144 , H01L21/67271
摘要: Disclosed is a die-bonding method having pick-and-probe features after wafer sawing where at least a die is probed and sorted according to different grades during a pick-and-place step performed after wafer sawing. A suction nozzle having a plurality of probes is utilized to probe the electrical terminals of the die. After picking, the suction nozzle is moved on a common moving path and the picked die is tested through the suction nozzle. The picked-and-probed die is moved and die-bonded to a die carrier loaded in a corresponding one of a plurality of die-bonding areas by moving the Suction nozzle on a chosen sorting path. Therefore, the die is probed and sorted during die-bonding processes. Higher graded dice at a same level are assembled on a same die carrier to form a higher graded semiconductor package.
摘要翻译: 公开了一种在晶片锯切之后具有拾取和探针特征的芯片接合方法,其中在晶片锯切之后执行的拾取和放置步骤期间,至少一个模具被探测并根据不同的等级进行分类。 使用具有多个探针的吸嘴来探测管芯的电端子。 拾取后,吸嘴在公共移动路径上移动,并通过吸嘴测试拾取的模具。 通过在所选择的分选路径上移动吸入喷嘴,将拾取和探测的模具移动并压模到装载在多个芯片接合区域中的相应的一个芯片接合区域中的模具载体。 因此,在芯片接合工艺期间探针和分选。 相同级别的较高分级骰子组装在相同的裸片载体上以形成更高级别的半导体封装。
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公开(公告)号:US20110127681A1
公开(公告)日:2011-06-02
申请号:US12958329
申请日:2010-12-01
申请人: Ching-Yu NI , Chia-Ming Cheng , Nan-Chun Lin
发明人: Ching-Yu NI , Chia-Ming Cheng , Nan-Chun Lin
IPC分类号: H01L23/485 , H01L21/60
CPC分类号: H01L23/498 , H01L21/78 , H01L23/3114 , H01L23/3192 , H01L24/06 , H01L2224/05624 , H01L2224/05647 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/1461 , H01L2924/15788 , H01L2924/16195 , H01L2924/16235 , H01L2924/00014 , H01L2924/00
摘要: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.
摘要翻译: 根据本发明的实施例提供了芯片封装及其制造方法。 芯片封装包括含有芯片并具有器件面积和外围焊盘区域的半导体衬底。 多个导电焊盘设置在外围接合焊盘区域处,并且钝化层形成在半导体衬底上以露出导电焊盘。 在器件区域的钝化层上形成绝缘保护层。 封装层设置在绝缘保护层上方以在外围接合焊盘区域露出导电焊盘和钝化层。 该方法包括在切割过程中形成绝缘保护层以覆盖多个导电焊盘,并且通过封装层的开口去除导电焊盘上的绝缘保护层。
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