Supply voltage level detector
    41.
    发明授权

    公开(公告)号:US06639419B2

    公开(公告)日:2003-10-28

    申请号:US10026673

    申请日:2001-12-27

    Applicant: Dae Han Kim

    Inventor: Dae Han Kim

    CPC classification number: G01R19/16538

    Abstract: The present invention relates to a supply voltage level detector. The supply voltage level detector includes a reference voltage generator for generating the reference voltage of a constant level depending on a control signal, a compare voltage generator for generating a compare voltage the variation ratio of which is higher than the supply voltage supplied from the outside depending on the control signal, and a comparator for comparing the reference voltage and the compare voltage depending on the control signal to output a given signal. The present invention constructs the compare voltage generator in the supply voltage level detector so that the variation of the compare voltage depending on the variation of the supply voltage becomes great. Therefore, the present invention can improve the sensing margin of the comparator for sensing the difference between the reference voltage and the compare voltage. Also, the present invention can prevent erroneous operation by a noise to accomplish a stable operation.

    Combined receiver and speaker
    42.
    发明授权
    Combined receiver and speaker 失效
    组合接收器和扬声器

    公开(公告)号:US06636611B2

    公开(公告)日:2003-10-21

    申请号:US10044932

    申请日:2002-01-15

    CPC classification number: H04R9/06 H04R1/06 H04R9/08

    Abstract: Disclosed herein is a combined receiver and speaker. The combined receiver and speaker has a diaphragm, a voice coil, and a chip resistor. The diaphragm generates sounds of a predetermined frequency through vibrations caused by a sound pressure in speaker and receiver modes. The voice coil vibrates the diaphragm using a magnetic field formed around a magnet attached to the diaphragm and generated by applied voice current. The chip resistor decreases the intensity of the applied voice current. The voice current is selectively applied to the voice coil such that the voice current is applied to the voice coil from speaker terminals in speaker mode, while the voice current is applied to the voice coil via the chip resistor from receiver terminals in receiver mode.

    Abstract translation: 这里公开了一种组合的接收器和扬声器。 组合的接收器和扬声器具有隔膜,音圈和片状电阻器。 隔膜通过扬声器和接收器模式中的声压引起的振动产生预定频率的声音。 音圈使用围绕安装在隔膜上的磁体形成的磁场振动隔膜,并通过施加的声音电流产生。 芯片电阻降低了施加的声音电流的强度。 语音电流被选择性地施加到音圈,使得语音电流从扬声器模式的扬声器端子施加到音圈,而语音电流经由来自接收器模式的接收器端子的芯片电阻器被施加到音圈。

    Method for making polysilicon thin film transistor having multiple gate electrodes
    43.
    发明授权
    Method for making polysilicon thin film transistor having multiple gate electrodes 有权
    制造具有多个栅电极的多晶硅薄膜晶体管的方法

    公开(公告)号:US06391693B1

    公开(公告)日:2002-05-21

    申请号:US09652187

    申请日:2000-08-31

    Abstract: Disclosed is a polysilicon thin film transistor capable of reducing leakage current in the off state and method for manufacturing the same. The polysilicon thin film transistor comprises a substrate; at least two gate electrodes formed on the substrate; an insulating layer coated on the gate electrodes; a channel layer formed on the gate insulating layer to cover the entire gate electrodes and made of polysilicon; an ion stopper formed on the channel layer corresponding to the gate electrode; impurity regions formed on the channel layer at both sides of the ion stopper; and source and drain electrodes contacted with outermost regions among the impurity regions respectively, wherein the outermost impurity regions are source and drain regions and the region between the gate electrodes is an auxiliary junction region for compensating ON current.

    Abstract translation: 公开了能够在关闭状态下减少漏电流的多晶硅薄膜晶体管及其制造方法。 多晶硅薄膜晶体管包括衬底; 形成在所述基板上的至少两个栅电极; 涂覆在栅电极上的绝缘层; 形成在所述栅绝缘层上以覆盖整个栅电极并由多晶硅制成的沟道层; 形成在与栅电极对应的沟道层上的离子塞; 形成在离子塞的两侧的沟道层上的杂质区; 源极和漏极分别与杂质区域中的最外部区域接触,其中最外面的杂质区域是源极和漏极区域,并且栅极电极之间的区域是用于补偿导通电流的辅助结区域。

    Polysilicon thin film transistor
    44.
    发明授权
    Polysilicon thin film transistor 有权
    多晶硅薄膜晶体管

    公开(公告)号:US6144042A

    公开(公告)日:2000-11-07

    申请号:US344179

    申请日:1999-06-24

    Abstract: Disclosed is a polysilicon thin film transistor capable of reducing leakage current in the off state and method for manufacturing the same. The polysilicon thin film transistor comprises a substrate; at least two gate electrodes formed on the substrate; an insulating layer coated on the gate electrodes; a channel layer formed on the gate insulating layer to cover the entire gate electrodes and made of polysilicon; an ion stopper formed on the channel layer corresponding to the gate electrode; impurity regions formed on the channel layer at both sides of the ion stopper; and source and drain electrodes contacted with outermost regions among the impurity regions respectively, wherein the outermost impurity regions are source and drain regions and the region between the gate electrodes is an auxiliary junction region for compensating ON current.

    Abstract translation: 公开了能够在关闭状态下减少漏电流的多晶硅薄膜晶体管及其制造方法。 多晶硅薄膜晶体管包括衬底; 形成在所述基板上的至少两个栅电极; 涂覆在栅电极上的绝缘层; 形成在栅极绝缘层上以覆盖整个栅电极并由多晶硅制成的沟道层; 形成在与栅电极对应的沟道层上的离子塞; 形成在离子塞的两侧的沟道层上的杂质区; 源极和漏极分别与杂质区域中的最外部区域接触,其中最外面的杂质区域是源极和漏极区域,并且栅极电极之间的区域是用于补偿导通电流的辅助结区域。

    METHOD FOR MANUFACTURING SINGLE-POLE ONLY USABLE MAGNET

    公开(公告)号:US20200030881A1

    公开(公告)日:2020-01-30

    申请号:US15580406

    申请日:2017-06-27

    Inventor: Jun-Bum AN

    Abstract: Provided is a method of manufacturing a magnet capable of using only a single pole, whereby a combination force between a permanent (or referred to as a magnet) and a yoke (or referred to as a shielding metal) can be improved without performing a manual bonding work therebetween and then the efficiency of subsequent processes, such as polishing and plating, after combination and completeness of a product can be improved.

    NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY DEVICE, AND OPERATING METHOD OF THE STORAGE DEVICE
    46.
    发明申请
    NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY DEVICE, AND OPERATING METHOD OF THE STORAGE DEVICE 有权
    非易失性存储器件,包括非易失性存储器件的存储器件和存储器件的操作方法

    公开(公告)号:US20150332770A1

    公开(公告)日:2015-11-19

    申请号:US14596677

    申请日:2015-01-14

    Applicant: Dae han KIM

    Inventor: Dae han KIM

    Abstract: A storage device includes a nonvolatile memory device and a memory controller is provided. The nonvolatile memory device includes a plurality of blocks. The memory controller is configured to detect, upon receiving a power-on signal, a partial block among the plurality of blocks. The partial block includes a first page incompletely programmed due to sudden power-off occurred to the storage device. The memory controller determines whether or not to perform a dummy program operation on the partial block, and programs a second page of the partial bock with dummy data. The first page is different from the second page.

    Abstract translation: 存储装置包括非易失性存储装置和存储器控制器。 非易失性存储器件包括多个块。 存储器控制器被配置为在接收到通电信号时检测多个块中的部分块。 部分块包括由于存储设备发生突然断电而不完全编程的第一页。 存储器控制器确定是否对部分块执行虚拟程序操作,并且用伪数据对部分块的第二页进行编程。 第一页与第二页不同。

    SELECTIVE FIN CUT PROCESS
    48.
    发明申请
    SELECTIVE FIN CUT PROCESS 有权
    选择切割过程

    公开(公告)号:US20140065828A1

    公开(公告)日:2014-03-06

    申请号:US13603725

    申请日:2012-09-05

    CPC classification number: H01L21/308 H01L21/823431 H01L29/66795

    Abstract: A process is provided for selective removal of one or more unwanted fins during FINFET device fabrication. In one aspect, the process includes: providing a conformal protective layer over multiple fin structures on a substrate; patterning one or more openings over the unwanted fin structure(s); and removing at least a top portion of the unwanted fin structure(s) exposed through the opening(s), the removing including removing at least a portion of the conformal protective layer over the unwanted fin structure(s) exposed through the opening(s). In enhanced aspects, the removing includes removing a hard mask from the at least one unwanted fin structure(s) exposed through the opening(s), and selectively removing semiconductor material of at least one unwanted fin structure(s). The conformal protective layer protects one or more remaining fin structures during the selective removal of the semiconductor material of the unwanted fin structure(s).

    Abstract translation: 提供了一种用于在FINFET器件制造期间选择性地去除一个或多个不需要的鳍片的工艺。 在一个方面,该方法包括:在衬底上的多个鳍结构上提供保形层; 在不需要的鳍结构上形成一个或多个开口; 以及去除通过所述开口暴露的不需要的翅片结构的至少顶部部分,所述移除包括将所述共形保护层的至少一部分去除在通过所述开口暴露的不需要的翅片结构之上 )。 在增强的方面,去除包括从暴露在开口中的至少一个不需要的鳍结构去除硬掩模,以及选择性地去除至少一个不需要的鳍结构的半导体材料。 共形保护层在选择性地去除不想要的鳍结构的半导体材料期间保护一个或多个剩余的鳍结构。

    MICROPROCESSOR BASED MULTI-JUNCTION DETECTOR SYSTEM AND METHOD OF USE
    49.
    发明申请
    MICROPROCESSOR BASED MULTI-JUNCTION DETECTOR SYSTEM AND METHOD OF USE 审中-公开
    基于微处理器的多功能检测系统及其使用方法

    公开(公告)号:US20140021335A1

    公开(公告)日:2014-01-23

    申请号:US13819695

    申请日:2011-08-31

    Abstract: The disclosure relates to a photodetector system including a multi-junction detector having a first junction configured to generate a first current when irradiated with a first optical radiation component within a first spectral range, and at least a second junction configured to generate a second current when irradiated with a second optical radiation component within a second spectral range that is different than the first spectral range. The photodetector system also comprises a microprocessor adapted to generate a first indication related to a first characteristic of the first optical radiation component based on the first current, and generate a second indication related to a second characteristic of the second optical radiation component based on the second current.

    Abstract translation: 本公开涉及一种包括多结检测器的光电检测器系统,该多结检测器具有第一连接点,其被配置为当在第一光谱范围内用第一光辐射分量照射时产生第一电流,并且至少第二连接被配置为在 在与第一光谱范围不同的第二光谱范围内用第二光辐射分量照射。 光电检测器系统还包括微处理器,其适于基于第一电流产生与第一光辐射分量的第一特性相关的第一指示,并且基于第二光辐射分量产生与第二光辐射分量的第二特性相关的第二指示 当前。

    Semiconductor integrated circuit and method for driving the same
    50.
    发明授权
    Semiconductor integrated circuit and method for driving the same 有权
    半导体集成电路及其驱动方法

    公开(公告)号:US08542044B2

    公开(公告)日:2013-09-24

    申请号:US13334241

    申请日:2011-12-22

    Abstract: A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

    Abstract translation: 半导体集成电路包括:延迟锁定环(DLL),被配置为通过将源时钟信号延迟第一延迟时间来获得锁定来产生DLL时钟信号,其中响应于更新来控制DLL的更新周期 锁定后的周期控制信号完成; 以及更新周期控制器,被配置为响应于源时钟信号和从DLL提供的多个控制信号,基于在DLL的循环路径中出现的第二延迟时间来生成更新周期控制信号。

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