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公开(公告)号：US20210304964A1
公开(公告)日：2021-09-30
申请号：US16942710
申请日：2020-07-29
Applicant: Faraday Technology Corp.
Inventor： Chia-Hui Tien , Tung-Tse Lin , Chih-Yuan Hung , Chih-Shiun Lu
Abstract: A capacitor includes a solid conductive plate, a first electrode, and a second electrode. The solid conductive plate is disposed above a substrate of a wafer. The solid conductive plate serves as a bottom plate of the capacitor. The first electrode is disposed above the solid conductive plate so that the solid conductive plate is located between the substrate and the first electrode. This first electrode serves as a top plate of the capacitor. The second electrode is disposed above the solid conductive plate, and is disposed beside the first electrode. The second electrode is electrically connected to the solid conductive plate.
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公开(公告)号：US11070351B1
公开(公告)日：2021-07-20
申请号：US17138910
申请日：2020-12-31
Applicant: Faraday Technology Corp.
Inventor： Raghu Nandan Chepuri
Abstract: The controller includes a first equalizer, a first detector, a second detector, a multiplexer, a data clock generator, and a second equalizer. The first equalizer is configured to receive and equalize the input data. The first detector is configured to detect optimum phase of the input data. The optimum phase of the input data represents the input data peak. The second detector is configured to generate an envelope data according to the input data and detect peak of envelop with respect to sampling phase. The data clock generator is configured to generate the recovered data clock. The second equalizer is configured to generate the recovered data. The multiplexer is configured to generate an offset value according to the input data peak and the envelope data peak. The offset value represents the recovered data clock having an optimum sampling frequency and an optimum sampling phase.
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公开(公告)号：US20200242058A1
公开(公告)日：2020-07-30
申请号：US16429070
申请日：2019-06-03
Applicant: Faraday Technology Corp.
Inventor： Shih-Ching Lin , Chun-Yuan Lai
Abstract: An interrupt management system and a management method thereof are provided. The interrupt management system includes a processor and an interrupt signal expanding controller. The processor receives a plurality of original interrupt signals. The interrupt signal expanding controller includes a decoder and an interrupt vector table. The decoder receives a plurality of expanding interrupt request signals, and decodes the expanding interrupt request signals to generate the original interrupt signals, where number of the expanding interrupt request signals is larger than number of the original interrupt signals. The interrupt vector table stores a plurality of interrupt vectors. The decoder reads one of the interrupt vectors to obtain an accessed interrupt vector according to the expanding interrupt request signals, and the interrupt signal expanding controller transmits the accessed interrupt vector to the processor.
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公开(公告)号：US10565381B2
公开(公告)日：2020-02-18
申请号：US16011650
申请日：2018-06-19
Applicant: Faraday Technology Corp.
Inventor： Chun-Yuan Lai , Chen-Chun Huang
Abstract: A method and apparatus for performing firmware programming on a microcontroller chip and the associated microcontroller chip are provided. The method includes: utilizing an integrated circuit (IC) programmer to generate a seed file including characteristic information of the IC programmer; utilizing an encoder to encrypt original data representing a program code at least according to the characteristic information, to generate an encryption version of the original data; utilizing the IC programmer to decrypt the encryption version of the original data according to the characteristic information, to generate the original data utilizing the IC programmer to encrypt the original data at least according to predetermined information, to generate another encryption version of the original data; utilizing the microcontroller chip to decrypt the other encryption version at least according to predetermined information stored in the microcontroller chip to generate the original data, and write the original data into a non-volatile (NV) memory.
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公开(公告)号：US20200028719A1
公开(公告)日：2020-01-23
申请号：US16286511
申请日：2019-02-26
Applicant: Faraday Technology Corp.
Inventor： Chia-Lin Hu
Abstract: An apparatus for performing baseline wander correction is provided. The apparatus may include: a plurality of filters, a common mode voltage generator, and a compensation circuit. The plurality of filters may filter a set of input signals to generate a set of differential signals, the common mode voltage generator may generate a common mode voltage between the set of differential signals, and the compensation circuit may perform compensation related to baseline wander correction on the set of differential signals. Multiple current paths of the compensation circuit are associated with each other. Through a first current path and a second current path within the current paths, the compensation circuit may perform charge or discharge control on a first capacitor and a second capacitor within the plurality of filters to dynamically adjust compensation amounts of the compensation, to reduce or eliminate a baseline wander effect of the set of differential signals.
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Patent Agency Ranking
公开(公告)号：US20190204368A1
公开(公告)日：2019-07-04
申请号：US15949044
申请日：2018-04-09
Applicant: Faraday Technology Corp.
Inventor： Tang-Long Chang , Chi-Sheng Liao , Jeng-Huang Wu
IPC: G01R21/133 , G05F3/16 , G06F1/26 , G06F13/40
CPC classification number: G01R21/133 , G05F3/16 , G06F1/266 , G06F13/4004
Abstract: A core power detection circuit and an associated input/output (I/O) control system are provided, where the core power detection circuit is utilized for performing power detection in the I/O control system to generate a core power detection signal to control the I/O control system, and the I/O control system operates according to a plurality of supply voltages with respect to a first reference voltage. The core power detection circuit includes: a reference power bias circuit arranged for generating a second reference voltage according to a first supply voltage of the plurality of supply voltages; and a comparison circuit, coupled to the reference power bias circuit, arranged for performing a comparison operation according to the second reference voltage and a second supply voltage of the plurality of supply voltages, to generate a third reference voltage.
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公开(公告)号：US20190122986A1
公开(公告)日：2019-04-25
申请号：US15860669
申请日：2018-01-03
Applicant: Faraday Technology Corp.
Inventor： Yi-Yeh Yang , Wang-Chin Chen , Po-Chen Lo , Shang-Ru Lin , Jen-Hsing Lin , Jin-Cheng Chen
IPC: H01L23/528 , H01L23/50 , H01L23/00
Abstract: A power distribution network adapted to provide power to a plurality of components in an integrated circuit is provided. The power distribution network includes a power distribution trunk path, a plurality of first power distribution branch paths, and a plurality of second power distribution branch paths. The power distribution trunk path is used for transmitting the power. A long axis direction of the power distribution trunk path is a first direction. The first power distribution branch paths and the second power distribution branch paths are electrically connected to the power distribution trunk path. A long axis direction of the first power distribution branch paths is a second direction different from the first direction. A long axis direction of the second power distribution branch paths is a third direction different from the first direction and the second direction.
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公开(公告)号：US10268226B1
公开(公告)日：2019-04-23
申请号：US15925781
申请日：2018-03-20
Applicant: Faraday Technology Corp.
Inventor： Wei Wang , Xiao-Dong Fei
Abstract: The disclosure provides a voltage generating device and a calibrating method thereof. The voltage generating device includes a bandgap circuit, a regulator circuit and a calibrating circuit. The bandgap circuit provides a bandgap voltage. The regulator circuit generates an output voltage correspondingly according to the bandgap voltage. In a first stage of a calibration period, the calibrating circuit detects the bandgap voltage, and correspondingly sets a resistance of at least one resistor of the bandgap circuit according to the bandgap voltage. In a second stage of the calibration period, the calibrating circuit detects the output voltage, and correspondingly sets a resistance of at least one resistor of the regulator circuit according to the output voltage.
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公开(公告)号：US10009017B2
公开(公告)日：2018-06-26
申请号：US14949888
申请日：2015-11-24
Applicant: Faraday Technology Corp.
Inventor： Pei-Yuan Chou , Jinn-Shyan Wang , Yeong-Jar Chang
IPC: G01R31/02 , H03L7/06 , H03K5/14 , G01R31/317 , H03K5/00
CPC classification number: H03K5/14 , G01R31/31709 , H03K2005/00019
Abstract: An apparatus for jitter measurement includes a first delay circuit, a second delay circuit, and a control circuit. The first delay circuit imposes a preliminary phase delay on an input signal to generate a delayed input signal. The second delay circuit operates with the first delay circuit to impose a fine phase delay on the delayed input signal. The control circuit controls amounts of delays imposed by the first and second delay circuits, and fine tunes the phase delay of the delayed input signal according to the amounts of delays respectively imposed by delay elements of the first and second delay circuits, and estimates or calculates a jitter window for the input signal according to adjustment results of the first and second delay circuits.
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公开(公告)号：US09948244B1
公开(公告)日：2018-04-17
申请号：US15385871
申请日：2016-12-21
Applicant: Faraday Technology Corp.
Inventor： Chih-Huang Lin
CPC classification number: H03F1/301 , H03F3/211 , H03F3/45201 , H03F3/45237 , H03F3/45273 , H03F3/4565 , H03F2200/555 , H03F2203/45336 , H03F2203/45372 , H03F2203/45508 , H03F2203/45594 , H03G1/0029 , H03G1/0088 , H03G3/30
Abstract: An amplifier with adjustable gain including a plurality of differential amplifiers and an output stage circuit is provided. Each of the differential amplifiers has at least one differential pair, two current terminals of each of the differential pairs are coupled by a connection structure, and the connection structure provides a negative feedback resistance. The differential amplifiers commonly receive a differential input signal pair, and output terminals of the differential amplifiers are coupled together. The output stage circuit inverts a voltage on the output terminals of the differential amplifiers to generate an output voltage. A direct current gain of the amplifier with adjustable gain is determined by adjusting at least one of working numbers of the differential amplifiers and the differential pairs.
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