公开(公告)号：US10134752B2

公开(公告)日：2018-11-20

申请号：US15393775

申请日：2016-12-29

Applicant: Kwang Soo Kim ,  Shin Hwan Kang ,  Jae Hoon Jang ,  Kohji Kanamori

Inventor： Kwang Soo Kim ,  Shin Hwan Kang ,  Jae Hoon Jang ,  Kohji Kanamori

IPC: H01L29/788 ,  H01L27/11582 ,  H01L27/11556 ,  G11C16/04

Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

公开(公告)号：US09991271B2

公开(公告)日：2018-06-05

申请号：US15345763

申请日：2016-11-08

Applicant: Shin-hwan Kang ,  Young-hwan Son ,  Dong-seog Eun ,  Chang-sup Lee ,  Jae-hoon Jang

Inventor： Shin-hwan Kang ,  Young-hwan Son ,  Dong-seog Eun ,  Chang-sup Lee ,  Jae-hoon Jang

IPC: H01L27/00 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.

公开(公告)号：US20170373089A1

公开(公告)日：2017-12-28

申请号：US15393775

申请日：2016-12-29

Applicant: Kwang Soo KIM ,  Shin Hwan KANG ,  Jae Hoon JANG ,  Kohji KANAMORI

Inventor： Kwang Soo KIM ,  Shin Hwan KANG ,  Jae Hoon JANG ,  Kohji KANAMORI

IPC: H01L27/11582 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11556 ,  G11C16/26

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L27/11556

Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

公开(公告)号：US20170365616A1

公开(公告)日：2017-12-21

申请号：US15485579

申请日：2017-04-12

Applicant: Shin-hwan KANG ,  Heon-kyu LEE ,  Kohji KANAMORI ,  Jae-duk LEE ,  Jae-hoon JANG ,  Kwang-soo KIM

Inventor： Shin-hwan KANG ,  Heon-kyu LEE ,  Kohji KANAMORI ,  Jae-duk LEE ,  Jae-hoon JANG ,  Kwang-soo KIM

IPC: H01L27/11582 ,  H01L29/04 ,  H01L27/1157 ,  H01L27/11524 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L29/16 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L29/16

Abstract: A vertical non-volatile memory device includes a substrate including a cell region; a lower insulating layer on the substrate; a lower wiring pattern in the cell region having a predetermined pattern and connected to the substrate through the lower insulating layer; and a plurality of vertical channel layers extending in a vertical direction with respect to a top surface of the substrate in the cell region, spaced apart from one another in a horizontal direction with respect to the top surface of the substrate, and electrically connected to the lower wiring pattern. The memory device also includes a plurality of gate electrodes stacked alternately with interlayer insulating layers in the cell region in the vertical direction along a side wall of a vertical channel layer and formed to extend in a first direction along the horizontal direction.

公开(公告)号：US20170358590A1

公开(公告)日：2017-12-14

申请号：US15345763

申请日：2016-11-08

Applicant: Shin-hwan KANG ,  Young-hwan SON ,  Dong-seog EUN ,  Chang-sup LEE ,  Jae-hoon JANG

Inventor： Shin-hwan KANG ,  Young-hwan SON ,  Dong-seog EUN ,  Chang-sup LEE ,  Jae-hoon JANG

IPC: H01L27/11556 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.

公开(公告)号：US09478291B2

公开(公告)日：2016-10-25

申请号：US15176917

申请日：2016-06-08

Applicant: Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

Inventor： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

Abstract translation: 具有垂直结构的非易失性存储器件包括具有垂直结构的NAND串。 NAND串包括多个存储单元，并且至少一对第一选择晶体管布置成与多个存储单元的第一端相邻。 多个字线耦合到NAND串的多个存储单元。 第一选择线通常连接到NAND串的至少一对第一选择晶体管。

公开(公告)号：US20150348637A1

公开(公告)日：2015-12-03

申请号：US14820895

申请日：2015-08-07

Applicant: Jinman HAN ,  Sun-Il SHIM ,  Donghyuk CHAE ,  Jae-Hoon JANG ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

Inventor： Jinman HAN ,  Sun-Il SHIM ,  Donghyuk CHAE ,  Jae-Hoon JANG ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

公开(公告)号：US08846421B2

公开(公告)日：2014-09-30

申请号：US13416202

申请日：2012-03-09

Applicant: Jin-Woo Lee ,  Jae-Hoon Jang ,  Dong-Hoon Lee ,  Jae-Ha Kim

Inventor： Jin-Woo Lee ,  Jae-Hoon Jang ,  Dong-Hoon Lee ,  Jae-Ha Kim

IPC: H01L21/00 ,  H01L33/62 ,  H01L33/60

CPC classification number: H01L33/62 ,  H01L33/60 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/8592 ,  H01L2924/181 ,  H01L2933/0066 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A method of manufacturing a lead frame for a light-emitting device package and a light-emitting device package are provided. The method of manufacturing a lead frame for a light-emitting device package includes: preparing a base substrate for the lead frame; forming diffusion roughness on the base substrate; and forming a reflective plating layer on the diffusion roughness formed base substrate.

Abstract translation: 提供一种制造发光器件封装引线框和发光器件封装的方法。 制造发光器件封装的引线框架的方法包括：准备用于引线框架的基底基板; 在基底基板上形成扩散粗糙度; 在扩散粗糙化基底上形成反射镀层。

公开(公告)号：US08736203B2

公开(公告)日：2014-05-27

申请号：US13423111

申请日：2012-03-16

Applicant: Jae Hoon Jang ,  Byung Woon Jang

Inventor： Jae Hoon Jang ,  Byung Woon Jang

IPC: H02P1/00 ,  H02P7/00 ,  H02P27/04

CPC classification number: B60L11/185 ,  B60L11/1803 ,  B60L11/1814 ,  B60L2210/30 ,  B60L2210/40 ,  B60L2220/54 ,  H02M7/217 ,  Y02T10/641 ,  Y02T10/7005 ,  Y02T10/7072 ,  Y02T10/7241 ,  Y02T90/121 ,  Y02T90/127 ,  Y02T90/128 ,  Y02T90/14

Abstract: An inverter/charger integrated device is provided. The inverter/charger integrated device includes: a three-phase motor; a rectifying unit configured to rectify AC power for charging a battery and output the rectified AC power to a neutral point of the three-phase motor; a rectifier/inverter integrated unit configured to be connected to the rectifying unit and charge the battery; and a control unit configured to control the charging of the battery and an operation of the three-phase motor.

Abstract translation: 提供逆变器/充电器集成器件。 逆变器/充电器集成器件包括：三相电机; 整流单元，被配置为对AC电力进行整流，以对电池充电并将整流的AC电力输出到三相电动机的中性点; 整流器/逆变器集成单元，被配置为连接到整流单元并对电池充电; 以及控制单元，被配置为控制电池的充电和三相电动机的操作。

公开(公告)号：US20130044545A1

公开(公告)日：2013-02-21

申请号：US13658461

申请日：2012-10-23

Applicant: Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

Inventor： Jae-hun Jeong ,  Han-soo Kim ,  Won-seok Cho ,  Jae-hoon Jang ,  Sun-il Shim

IPC: G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L23/5226 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/7881

Abstract: A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

Abstract translation: 具有垂直结构的非易失性存储器件包括具有垂直结构的NAND串。 NAND串包括多个存储单元，并且至少一对第一选择晶体管布置成与多个存储单元的第一端相邻。 多个字线耦合到NAND串的多个存储单元。 第一选择线通常连接到NAND串的至少一对第一选择晶体管。