公开(公告)号：US20150348637A1

公开(公告)日：2015-12-03

申请号：US14820895

申请日：2015-08-07

申请人： Jinman HAN ,  Sun-Il SHIM ,  Donghyuk CHAE ,  Jae-Hoon JANG ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

发明人： Jinman HAN ,  Sun-Il SHIM ,  Donghyuk CHAE ,  Jae-Hoon JANG ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

摘要： Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

公开(公告)号：US20170330632A1

公开(公告)日：2017-11-16

申请号：US15664303

申请日：2017-07-31

申请人： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

发明人： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC分类号： G11C16/34 ,  G11C16/14 ,  G11C16/04 ,  G11C16/12 ,  G11C16/10 ,  G11C16/08 ,  H01L27/11582 ,  G11C16/26 ,  H01L27/1157

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

摘要： Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US20160284419A1

公开(公告)日：2016-09-29

申请号：US15176269

申请日：2016-06-08

申请人： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

发明人： Sun-Il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

摘要： Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

摘要翻译： 非易失性存储器件，其操作方法和包括其的存储器系统。 非易失性存储器件可以包括存储单元阵列和字线驱动器。 存储单元阵列可以包括多个存储单元。 字线驱动器可以被配置为分别将字线电压施加到连接到多个存储器单元的多个字线。 字线电压的大小可以根据多个字线的位置来确定。

公开(公告)号：US20150380093A1

公开(公告)日：2015-12-31

申请号：US14849029

申请日：2015-09-09

申请人： Sun-il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

发明人： Sun-il SHIM ,  Jae-Hoon JANG ,  Donghyuk CHAE ,  Youngho LIM ,  Hansoo KIM ,  Jaehun JEONG

IPC分类号： G11C16/12 ,  G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

摘要： Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

摘要翻译： 非易失性存储器件，其操作方法和包括其的存储器系统。 非易失性存储器件可以包括存储单元阵列和字线驱动器。 存储单元阵列可以包括多个存储单元。 字线驱动器可以被配置为分别将字线电压施加到连接到多个存储器单元的多个字线。 字线电压的大小可以根据多个字线的位置来确定。

公开(公告)号：US20160284416A1

公开(公告)日：2016-09-29

申请号：US15175173

申请日：2016-06-07

申请人： Jinman HAN ,  Donghyuk CHAE

发明人： Jinman HAN ,  Donghyuk CHAE

IPC分类号： G11C16/16 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

摘要： Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

公开(公告)号：US20150302927A1

公开(公告)日：2015-10-22

申请号：US14788109

申请日：2015-06-30

申请人： Jinman HAN ,  Donghyuk CHAE

发明人： Jinman HAN ,  Donghyuk CHAE

IPC分类号： G11C16/16

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

摘要： Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

摘要翻译： 非易失性存储器件，其操作方法和包括该非易失性存储器件的存储器系统。 在操作方法中，连接到位线的第一串的接地选择线可以浮置。 可以将擦除禁止电压施加到连接到位线的第二串的接地选择线。 可以将擦除操作电压施加到第一和第二串。

公开(公告)号：US20150138882A1

公开(公告)日：2015-05-21

申请号：US14579755

申请日：2014-12-22

申请人： Jinman HAN ,  Donghyuk CHAE

发明人： Jinman HAN ,  Donghyuk CHAE

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26

摘要： Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.

公开(公告)号：US20130279262A1

公开(公告)日：2013-10-24

申请号：US13920691

申请日：2013-06-18

申请人： ChiWeon YOON ,  Donghyuk CHAE ,  Sang-Wan NAM ,  Sung-Won YUN

发明人： ChiWeon YOON ,  Donghyuk CHAE ,  Sang-Wan NAM ,  Sung-Won YUN

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3418 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Non-volatile memory device channel boosting methods in which at least two strings are connected to one bit line, the channel boosting methods including applying an initial channel voltage to channels of strings in a selected memory block, floating inhibit strings each having an un-programmed cell among the strings, and boosting channels of the floated inhibit strings.

摘要翻译： 非易失性存储器件通道升压方法，其中至少两个串连接到一个位线，所述通道升压方法包括将初始通道电压施加到所选存储器块中的串的通道，每个具有未编程的浮动禁止串 字符串之间的单元格，以及浮动禁止字符串的增强通道。

公开(公告)号：US20120314496A1

公开(公告)日：2012-12-13

申请号：US13593036

申请日：2012-08-23

申请人： Donghyuk CHAE

发明人： Donghyuk CHAE

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5646

摘要： Memory systems include at least one nonvolatile memory array having a plurality of rows of nonvolatile multi-bit (e.g., N-bit, where N>2) memory cells therein. A control circuit is also provided, which is electrically coupled to the nonvolatile memory array. The control circuit is configured to program at least two pages of data into a first row of nonvolatile multi-bit memory cells in the nonvolatile memory array using a first sequence of read voltages to verify accuracy of the data stored within the first row. The control circuit is also configured to read the at least two pages of data from the first row using a second sequence of read voltages that is different from the first sequence of read voltages. Each of the read voltages in the first sequence of read voltages may be equivalent in magnitude to a corresponding read voltage in the second sequence of read voltages.

摘要翻译： 存储器系统包括至少一个非易失性存储器阵列，其中具有多行非易失性多位（例如N位，其中N≥2）个存储单元。 还提供了一种控制电路，其电耦合到非易失性存储器阵列。 控制电路被配置为使用第一读取电压序列将至少两页数据编程到非易失性存储器阵列中的第一行非易失性多位存储器单元中，以验证存储在第一行内的数据的精度。 控制电路还被配置为使用与第一读取电压序列不同的第二读取电压序列从第一行中读取至少两页的数据。 第一读取电压序列中的每个读取电压的幅度可以在第二读取电压序列中与相应的读取电压相等。

公开(公告)号：US20120201080A1

公开(公告)日：2012-08-09

申请号：US13368769

申请日：2012-02-08

申请人： Kyung-Hwa KANG ,  Sang-Wan NAM ,  Donghyuk CHAE ,  ChiWeon YOON

发明人： Kyung-Hwa KANG ,  Sang-Wan NAM ,  Donghyuk CHAE ,  ChiWeon YOON

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/08

CPC分类号： G11C16/0483 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/24 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

摘要： Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.

摘要翻译： 非易失性存储器件包括具有连接在衬底和多个位线之间并由选择线选择的多个单元串的存储单元阵列，以及配置成在至少两个方向上驱动选择线的选通电路。