公开(公告)号：US20070115727A1

公开(公告)日：2007-05-24

申请号：US11465323

申请日：2006-08-17

申请人： Yong-Taek JEONG ,  Jin-Yub LEE

发明人： Yong-Taek JEONG ,  Jin-Yub LEE

IPC分类号： G11C11/34

CPC分类号： G11C5/145 ,  G11C16/30

摘要： A flash memory device may include a pump, a regulator to control the pump so that an output voltage of the pump is substantially maintained at a target voltage, and a control circuit to control the regulator so that the pump selectively generates a program voltage or an erase voltage. In some embodiments, the output voltage of the pump may be stepped in response to program loop iterations during a program operation, or set to a target voltage during an erase operation.

摘要翻译： 闪存器件可以包括泵，用于控制泵的调节器，使得泵的输出电压基本上保持在目标电压，以及控制电路以控制调节器，使得泵选择性地产生编程电压或 擦除电压。 在一些实施例中，泵的输出电压可以在编程操作期间响应于程序循环迭代而阶梯式，或者在擦除操作期间被设置为目标电压。

公开(公告)号：US20070109862A1

公开(公告)日：2007-05-17

申请号：US11599434

申请日：2006-11-15

申请人： Jin-Kook Kim ,  Jin-Yub Lee

发明人： Jin-Kook Kim ,  Jin-Yub Lee

IPC分类号： G11C11/34

CPC分类号： G11C8/08 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30

摘要： In one aspect, a word line enable method in a flash memory device includes driving a signal line corresponding to a selected word line with a word line voltage, and stepwise increasing a gate voltage of a switch transistor connected between the selected word line and the signal line during a program execute period.

摘要翻译： 一方面，闪速存储装置中的字线使能方法包括用字线电压驱动与选定字线对应的信号线，并且逐步增加连接在选定字线与信号之间的开关晶体管的栅极电压 在程序执行期间。

公开(公告)号：US07203791B2

公开(公告)日：2007-04-10

申请号：US10830940

申请日：2004-04-22

申请人： Jin-Yub Lee

发明人： Jin-Yub Lee

IPC分类号： G06F12/12

CPC分类号： G11C16/105 ,  G11C16/102

摘要： The disclosure is NAND flash memory device with a partial copy-back mode, comprised of a cell array constructed of pages, a page buffer block composed of page buffers storing data in correspondence with the pages, a selection circuit for designating one or more pages to be initialized in the partial copy-back mode, and a control circuit for generating control signals to operate the page buffers and the selection circuit.

摘要翻译： 本公开是具有部分复制模式的NAND闪速存储器件，包括由页构成的单元阵列，由与页相对应的数据的页缓冲器组成的页缓冲块，用于指定一页或多页的选择电路 以部分复制模式被初始化，以及用于产生控制信号以操作页面缓冲器和选择电路的控制电路。

公开(公告)号：US20070025159A1

公开(公告)日：2007-02-01

申请号：US11478580

申请日：2006-07-03

申请人： Chul-Ho Lee ,  Jin-Yub Lee

发明人： Chul-Ho Lee ,  Jin-Yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/3454

摘要： A non-volatile memory device comprises a memory cell array having a plurality of non-volatile memory cells arranged in rows and columns. Selected memory cells are programmed by applying program voltages thereto. Next, data bits stored in the selected cells are read. Then, a first column scan operation is performed to determine whether any of the selected memory cells is inadequately programmed. Upon determining that at least one of the selected memory cells is inadequately programmed, a second column scan operation is performed to detect a total number of the selected memory cells that are inadequately programmed. Upon determining that the total number of the selected memory cells that are inadequately programmed is less than a number that can be corrected by an error correcting circuit, the program operation terminates with a program pass status.

摘要翻译： 非易失性存储器件包括具有以行和列排列的多个非易失性存储单元的存储单元阵列。 所选存储单元通过向其施加编程电压而被编程。 接下来，读取存储在所选择的单元中的数据位。 然后，执行第一列扫描操作以确定所选择的存储单元中的任何一个是否未被编程。 在确定所选择的存储器单元中的至少一个存储器单元不充分地被编程时，执行第二列扫描操作以检测未编程的所选存储器单元的总数。 在确定编程不正确的所选存储器单元的总数小于可由纠错电路校正的数量时，程序操作以程序通过状态终止。

公开(公告)号：US20070014184A1

公开(公告)日：2007-01-18

申请号：US11383064

申请日：2006-05-12

申请人： Ho-Kil LEE ,  Jin-Yub LEE

发明人： Ho-Kil LEE ,  Jin-Yub LEE

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C16/0483 ,  G11C16/08

摘要： A wordline decoder for a non-volatile memory device includes a first inverter to invert a block selection signal into a first inverted result on a first node, a second inverter to invert the signal on the first node into a second inverted result on a second node, a first and a second transistor, each coupled to a power supply, coupled in series between the second node and a third node, a third transistor coupled between the third node and a fourth node having a gate coupled to the third node, a fourth transistor coupled between a high voltage supply and a fifth node having a source coupled to the high voltage supply and a gate coupled to the third node, and a fifth transistor coupled between the fifth node and the third node having a gate coupled to the first node.

摘要翻译： 用于非易失性存储器件的字线解码器包括：第一反相器，用于将块选择信号反转到第一节点上的第一反相结果;第二反相器，用于将第一节点上的信号反转为第二节点上的第二反相结果 ，第一和第二晶体管，每个耦合到电源，串联耦合在第二节点和第三节点之间;第三晶体管，耦合在第三节点和第四节点之间，第四节点具有耦合到第三节点的栅极;第四晶体管，第四晶体管， 耦合在高压电源和耦合到高压电源的源极的第五节点和耦合到第三节点的栅极之间的晶体管，以及耦合在第五节点和第三节点之间的第五晶体管，其具有耦合到第一节点 。

公开(公告)号：US20050248992A1

公开(公告)日：2005-11-10

申请号：US10998987

申请日：2004-11-30

申请人： Sang-Won Hwang ,  Jin-Yub Lee ,  Bum-Soo Kim ,  Kwang-Yoon Lee ,  Cha-Nik Park

发明人： Sang-Won Hwang ,  Jin-Yub Lee ,  Bum-Soo Kim ,  Kwang-Yoon Lee ,  Cha-Nik Park

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/3454

摘要： Method and device for programming control information, such as a flag, a control flag, a mark, or a control mark. The method and device may perform a lower-speed programming of a given cell type in a first area of memory array, confirm a result of the lower-speed programming of the given cell type in the first area of memory array, and perform a higher-speed programming of the given cell type in a second area of memory array after confirming the result of the lower-speed programming, wherein an initial programming voltage of the higher-speed programming may be different from that of the lower-speed programming. The first and second programming may be different, for example, the first programming may be a lower-speed operation, such as the writing of data, and the second programming may be a higher-speed operation, such as the writing of control information. The first and second programming methods may also be different, for example, the first programming method may be a programming method that does not permit over-programming and the second programming method may be a programming method that does permit over-programming.

摘要翻译： 用于编程控制信息的方法和装置，例如标志，控制标志，标记或控制标记。 该方法和装置可以在存储器阵列的第一区域中执行给定小区类型的低速编程，确认在存储器阵列的第一区域中给定小区类型的较低速度编程的结果，并且执行更高的 在确认低速编程的结果之后，在存储器阵列的第二区域中对给定单元类型的速度编程，其中较高速度编程的初始编程电压可能与低速编程的初始编程电压不同。 第一和第二编程可以是不同的，例如，第一编程可以是诸如写入数据的低速操作，并且第二编程可以是诸如写入控制信息的更高速的操作。 第一和第二编程方法也可以不同，例如，第一编程方法可以是不允许过度编程的编程方法，并且第二编程方法可以是允许过度编程的编程方法。

公开(公告)号：US20170117054A1

公开(公告)日：2017-04-27

申请号：US15295536

申请日：2016-10-17

申请人： VENKATARAMANA GANGASANI ,  JIN-YUB LEE ,  SUNGWHAN SEO ,  WON-TAE KIM ,  DOJEON LEE ,  YOHAN LEE

发明人： VENKATARAMANA GANGASANI ,  JIN-YUB LEE ,  SUNGWHAN SEO ,  WON-TAE KIM ,  DOJEON LEE ,  YOHAN LEE

IPC分类号： G11C16/34 ,  G11C16/26 ,  G11C16/16 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08

CPC分类号： G11C16/3431 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

摘要： A nonvolatile memory device includes a voltage generating circuit configured to generate voltages applied to word lines corresponding to a selected memory block among memory blocks. The voltage generating circuit includes voltage source lines having linear voltages, a first voltage generating unit configured to generate a first voltage and apply the generated first voltage to a first voltage source line among the voltage source lines, a second voltage generating unit configured to generate a second voltage and apply the generated second voltage to a second voltage source line among the voltage source lines, and a linear voltage generator having a resistor string connected between the first voltage source line and the second voltage source line. At least one of the voltage source lines has a voltage distributed between the first voltage and the second voltage.

公开(公告)号：US08760919B2

公开(公告)日：2014-06-24

申请号：US13598892

申请日：2012-08-30

申请人： Jung-Ho Song ,  Jin-Yub Lee ,  Jae-Woo Im ,  Seung-Jae Lee ,  Sang-So Park

发明人： Jung-Ho Song ,  Jin-Yub Lee ,  Jae-Woo Im ,  Seung-Jae Lee ,  Sang-So Park

IPC分类号： G11C11/56 ,  G11C16/04

CPC分类号： G11C11/56 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3404 ,  G11C2211/56

摘要： A method is provided for reading data in a nonvolatile memory device. The method includes performing a first read operation on multiple multi-level memory cells (MLCs), performing a first sensing operation on at least one flag cell corresponding to the MLCs, selectively performing a second read operation on the MLCs based on a result of the first sensing operation, and performing a second sensing operation on the at least one flag cell when the second read operation is performed. Read data is output based on results of the first read operation and the first sensing operation when the second read operation is not performed, and the read data is output based on result of the first read operation, the first sensing operation, the second read operation and the second sensing operation when the second read operation is performed. The read data corresponds to programmed data in the MLCs.

摘要翻译： 提供了一种用于在非易失性存储器件中读取数据的方法。 该方法包括：对多个多电平存储器单元（MLC），在对应于MLC中的至少一个标志单元，基于所述结果选择性地执行上的MLC的第二读取操作执行第一读出操作的第一次读操作 第一感测操作，并且当执行第二读取操作时对所述至少一个标志单元执行第二感测操作。 在不执行第二读取操作时，基于第一读取操作和第一感测操作的结果输出读取数据，并且基于第一读取操作，第一感测操作，第二读取操作的结果来输出读取数据 以及执行第二读取操作时的第二感测操作。 读取数据对应于MLC中的编程数据。

公开(公告)号：US07772910B2

公开(公告)日：2010-08-10

申请号：US12045125

申请日：2008-03-10

申请人： Chul-Ho Lee ,  Jin-Yub Lee

发明人： Chul-Ho Lee ,  Jin-Yub Lee

IPC分类号： G06F1/04

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  Y02D10/126 ,  Y02D10/14

摘要： An internal clock generator, system and method of generating the internal clock are disclosed. The method comprises detecting the level of an operating voltage within the system, comparing the level of the operating voltage to a target voltage level and generating a corresponding detection signal, and selecting between a normal clock and an alternate clock having a period longer than the period of the normal clock in relation to the detection signal and generating an internal clock on the basis of the selection.

摘要翻译： 公开了一种产生内部时钟的内部时钟发生器，系统和方法。 该方法包括检测系统内的工作电压的电平，将工作电压的电平与目标电压电平进行比较，并产生相应的检测信号，以及选择正常时钟和具有比周期长的周期的备用时钟 的相对于检测信号的正常时钟，并且基于该选择产生内部时钟。

公开(公告)号：US07719897B2

公开(公告)日：2010-05-18

申请号：US11297779

申请日：2005-12-07

申请人： Chul-Ho Lee ,  Jin-Yub Lee

发明人： Chul-Ho Lee ,  Jin-Yub Lee

IPC分类号： G11C16/26

CPC分类号： G11C16/3454 ,  G11C16/04 ,  G11C16/10 ,  G11C29/52 ,  G11C29/804 ,  G11C2029/0409 ,  G11C2216/14

摘要： A non-volatile memory device includes page buffers arranged in groups, each group being coupled to a corresponding data output line so that data from more than one of the page buffers in each group may be simultaneously represented on the corresponding data output line during a program verification operation. Page buffers may be arranged in repair units with data from more than one page buffer simultaneously coupled to a data output line during a column scan operation.

摘要翻译： 非易失性存储器件包括以组为单位布置的页缓冲器，每个组耦合到对应的数据输出线，使得每个组中来自多个页缓冲器中的数据可以在程序期间在相应的数据输出行上同时表示 验证操作。 在列扫描操作期间，页缓冲器可以被布置成具有来自多于一个页缓冲器的数据同时耦合到数据输出线的修复单元。