公开(公告)号：US08627251B2

公开(公告)日：2014-01-07

申请号：US13455186

申请日：2012-04-25

Applicant: Jui-Long Chen ,  Hui-Yun Chao ,  Yen-Di Tsen ,  Jong-I Mou

Inventor： Jui-Long Chen ,  Hui-Yun Chao ,  Yen-Di Tsen ,  Jong-I Mou

IPC: G06F17/50

CPC classification number: H01L22/20 ,  H01L22/10 ,  H01L22/12 ,  H01L22/14 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

Abstract: A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process.

Abstract translation: 提供了一种自动检测半导体晶片工艺的故障模式的系统和方法。 该方法包括接收从测试多个半导体晶片收集的测试数据集，为每个晶片形成相应的晶片图，确定每个相应的晶片图是否包括一个或多个相应的对象，选择被确定为包括的晶片图 一个或多个相应的对象，选择一个或多个对象索引，用于在每个相应的选定的晶片图中选择相应的对象，确定每个相应选择的晶片图中的多个对象索引值，在每个相应选定的晶片图中选择一个对象， 各个所选晶片中的每一个的相应特征，对各个所选晶片图中的每一个分类各自的图案，并使用相应的晶片指纹来调整半导体制造工艺的一个或多个参数。

公开(公告)号：US20130335109A1

公开(公告)日：2013-12-19

申请号：US13495421

申请日：2012-06-13

Applicant: Jui-Long Chen ,  Chien-Chih Liao ,  Tseng Chin Lo ,  Hui-Yun Chao ,  Ta-Yung Lee ,  Jong-I Mou ,  Chin-Hsiang Lin

Inventor： Jui-Long Chen ,  Chien-Chih Liao ,  Tseng Chin Lo ,  Hui-Yun Chao ,  Ta-Yung Lee ,  Jong-I Mou ,  Chin-Hsiang Lin

IPC: G01R31/26 ,  H01L29/06

CPC classification number: G01R1/07364 ,  G01R1/06705 ,  G01R31/2887 ,  G01R31/2891 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/5446 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.

Abstract translation: 公开了一种用于将诸如晶片级测试探针之类的探针与晶片接点对准的系统和方法。 一种示例性方法包括在晶片测试系统处接收包含多个对准触点的晶片和包含多个探针点的探针卡。 接收到历史偏移校正。 基于历史偏移校正，确定探针卡相对于晶片的取向值。 使用取向值将探针卡与晶片对准，以试图使第一探针点与第一对准触点接触。 评估第一探针点和第一对准接触点的连接性。 使用对准的探针卡进行晶片的电气测试，并且基于取向值更新历史偏移校正。

公开(公告)号：US08239056B2

公开(公告)日：2012-08-07

申请号：US12616681

申请日：2009-11-11

Applicant: Chih-Wei Hsu ,  Yu-Jen Cheng ,  Wen-Pin Liu ,  Shun-Ping Wang ,  Shin-Rung Lu ,  Jo Fei Wang ,  Jong-I Mou ,  Andy Tsen ,  Chun-Hsien Lin

Inventor： Chih-Wei Hsu ,  Yu-Jen Cheng ,  Wen-Pin Liu ,  Shun-Ping Wang ,  Shin-Rung Lu ,  Jo Fei Wang ,  Jong-I Mou ,  Andy Tsen ,  Chun-Hsien Lin

IPC: G06F19/00

CPC classification number: H01L21/67253 ,  G05B19/41865 ,  H01L21/67276 ,  Y02P90/20

Abstract: The present disclosure provides a semiconductor manufacturing method. The method includes providing product data of a product, the product data including a sensitive product parameter; searching existing products according to the sensitive product parameter to identify a relevant product from the existing products; determining an initial value of a processing model parameter to the product using corresponding data of the relevant product; assigning the initial value of the processing model parameter to a processing model associated with a manufacturing process; thereafter, tuning a processing recipe using the processing model; and performing the manufacturing process to a semiconductor wafer using the processing recipe.

Abstract translation: 本发明提供一种半导体制造方法。 该方法包括提供产品的产品数据，产品数据包括敏感产品参数; 根据敏感产品参数搜索现有产品，从现有产品中识别相关产品; 使用相关产品的相应数据确定产品的处理模型参数的初始值; 将处理模型参数的初始值分配给与制造过程相关联的处理模型; 此后，使用该处理模型调整处理配方; 以及使用所述处理配方对所述半导体晶片进行制造处理。

公开(公告)号：US08219341B2

公开(公告)日：2012-07-10

申请号：US12411680

申请日：2009-03-26

Applicant: Andy Tsen ,  Sunny Wu ,  Wang Jo Fei ,  Jong-I Mou

Inventor： Andy Tsen ,  Sunny Wu ,  Wang Jo Fei ,  Jong-I Mou

IPC: G06F19/00

CPC classification number: H01L22/20 ,  H01L22/14

Abstract: System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing an inter-metal (“IM”) WAT on a plurality of processed wafer lots; selecting a subset of the plurality of wafer lots using a lot sampling process; and selecting a sample wafer group using the wafer lot subset, wherein IM WAT is performed on wafers of the sample wafer group to obtain IM WAT data therefore. The method further comprises estimating final WAT data for all wafers in the processed wafer lots from IM WAT data obtained for the sample wafer group and providing the estimated final WAT data to a WAT APC process for controlling processes.

Abstract translation: 描述了实现晶片验收测试（“WAT”）高级过程控制（“APC”）的系统和方法。 在一个实施例中，该方法包括在多个经处理的晶片批次上执行金属间（“IM”）WAT; 使用批次采样处理来选择所述多个晶片批次的子集; 以及使用晶片批次子集选择样品晶片组，因此在样品晶片组的晶片上执行IM WAT以获得IM WAT数据。 该方法还包括从针对样品晶片组获得的IM WAT数据估计经处理的晶片批次中的所有晶片的最终WAT数据，并将估计的最终WAT数据提供给用于控制过程的WAT APC过程。

公开(公告)号：US08205173B2

公开(公告)日：2012-06-19

申请号：US12818003

申请日：2010-06-17

Applicant: Sunny Wu ,  Yen-Di Tsen ,  Monghsung Chuang ,  Fu-Min Huang ,  Jo Fei Wang ,  Jong-I Mou

Inventor： Sunny Wu ,  Yen-Di Tsen ,  Monghsung Chuang ,  Fu-Min Huang ,  Jo Fei Wang ,  Jong-I Mou

IPC: G06F17/50 ,  G06F19/00 ,  G06F11/00 ,  G01R31/00

CPC classification number: G01R31/2894

Abstract: A method includes providing a plurality of failure dies, and performing a chip probing on the plurality of failure dies to generate a data log comprising electrical characteristics of the plurality of failure dies. An automatic net tracing is performed to trace failure candidate nodes in the failure dies. A failure layer analysis is performed on results obtained from the automatic net tracing. Physical failure analysis (PFA) samples are selected from the plurality of failure dies using results obtained in the step of performing the failure layer analysis.

Abstract translation: 一种方法包括提供多个故障管芯，并对多个故障管芯进行芯片探测以产生包括多个故障管芯的电气特性的数据记录。 执行自动网络跟踪以跟踪故障模块中的故障候选节点。 对从自动网络跟踪获得的结果执行故障层分析。 使用在执行故障层分析的步骤中获得的结果从多个故障模具中选择物理故障分析（PFA）样本。

公开(公告)号：US20120129431A1

公开(公告)日：2012-05-24

申请号：US12953584

申请日：2010-11-24

Applicant: KEUNG HUI ,  Jin-Ning Sung ,  Huang Soon Kang ,  Yen-Di Tsen ,  Jong-I Mou

Inventor： KEUNG HUI ,  Jin-Ning Sung ,  Huang Soon Kang ,  Yen-Di Tsen ,  Jong-I Mou

IPC: B24B1/00 ,  B24B51/00

CPC classification number: H01L21/30625 ,  B24B37/005 ,  B24B37/042 ,  B24B37/107 ,  B24B49/02 ,  B24B49/04 ,  B24B49/16 ,  B24B51/00 ,  H01L22/12 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.

Abstract translation: 公开了一种用于提供多头化学机械抛光（CMP）工艺的目标厚度和表面轮廓均匀性控制的装置和方法。 一种示例性方法包括提供至少两个晶片; 确定所述至少两个晶片中的每一个的表面轮廓; 基于所述至少两个晶片的表面轮廓确定用于化学机械抛光（CMP）工艺的操作模式; 基于所述操作模式确定所述至少两个晶片中的每一个的CMP抛光配方; 以及基于所确定的CMP抛光配方在所述至少两个晶片上执行CMP处理。

公开(公告)号：US08108060B2

公开(公告)日：2012-01-31

申请号：US12465064

申请日：2009-05-13

Applicant: Andy Tsen ,  Jo Fei Wang ,  Po-Feng Tsai ,  Ming-Yu Fan ,  Jill Wang ,  Jong-I Mou ,  Sunny Wu

Inventor： Andy Tsen ,  Jo Fei Wang ,  Po-Feng Tsai ,  Ming-Yu Fan ,  Jill Wang ,  Jong-I Mou ,  Sunny Wu

IPC: G06F19/00 ,  G06F17/18 ,  G06F11/30 ,  G01N37/00

CPC classification number: G05B13/048 ,  G05B19/41875 ,  Y02P90/22 ,  Y02P90/86

Abstract: System and method for implementing wafer acceptance test (“WAT”) advanced process control (“APC”) are described. In one embodiment, the method comprises performing a key process on a sample number of wafers of a lot of wafers; performing a key inline measurement related to the key process to produce metrology data for the wafers; predicting WAT data from the metrology data using an inline-to-WAT model; and using the predicted WAT data to tune a WAT APC process for controlling a tuning process or a process APC process.

Abstract translation: 描述了实现晶片验收测试（“WAT”）高级过程控制（“APC”）的系统和方法。 在一个实施例中，该方法包括对大量晶片的晶片的样本数进行密钥处理; 执行关键过程的关键在线测量以产生晶片的测量数据; 使用直线到WAT模型预测来自计量数据的WAT数据; 并且使用预测的WAT数据来调整用于控制调谐过程或过程APC过程的WAT APC过程。

公开(公告)号：US20120009692A1

公开(公告)日：2012-01-12

申请号：US12831699

申请日：2010-07-07

Applicant: Keung Hui ,  Chun-Lin Chang ,  Jong-I Mou

Inventor： Keung Hui ,  Chun-Lin Chang ,  Jong-I Mou

IPC: H01L21/66 ,  H01J37/317 ,  H01J37/20

CPC classification number: C23C14/48 ,  H01J37/302 ,  H01J37/304 ,  H01J37/3171 ,  H01J2237/30461 ,  H01J2237/31703 ,  H01L21/265 ,  H01L22/14

Abstract: A system and method for controlling a dosage profile is disclosed. An embodiment comprises separating a wafer into components of a grid array and assigning each of the grid components a desired dosage profile based upon a test to compensate for topology differences between different regions of the wafer. The desired dosages are decomposed into directional dosage components and the directional dosage components are translated into scanning velocities of the ion beam for an ion implanter. The velocities may be fed into an ion implanter to control the wafer-to-beam velocities and, thereby, control the implantation.

Abstract translation: 公开了一种用于控制剂量分布的系统和方法。 一个实施例包括将晶片分离成网格阵列的组件，并且基于测试来分配每个网格组件所需的剂量分布，以补偿晶片的不同区域之间的拓扑差异。 期望的剂量被分解为定向剂量组分，并且定向剂量组分转化成用于离子注入机的离子束的扫描速度。 速度可以被馈送到离子注入机中以控制晶片到光束的速度，从而控制注入。

公开(公告)号：US08082055B2

公开(公告)日：2011-12-20

申请号：US12499345

申请日：2009-07-08

Applicant: Chun-Hsien Lin ,  Andy Tsen ,  Jui-Long Chen ,  Sunny Wu ,  Jong-I Mou ,  Chia-Hung Huang

Inventor： Chun-Hsien Lin ,  Andy Tsen ,  Jui-Long Chen ,  Sunny Wu ,  Jong-I Mou ,  Chia-Hung Huang

IPC: G06F19/00

CPC classification number: G06Q10/06 ,  G06Q30/0202

Abstract: A method for providing a bin ratio forecast at an early stage of integrated circuit device manufacturing processes is disclosed. The method comprises collecting historical data from one or more processed wafer lots; collect measurement data from one or more skew wafer lots; generating an estimated baseline distribution from the collected historical data and collected measurement data; generating an estimated performance distribution based on one or more specified parameters and the generated estimated baseline distribution; determining a bin ratio forecast by applying a bin definition and a yield degradation factor estimation to the generated estimated performance distribution; determining one or more production targets based on the bin ratio forecast; and processing one or more wafers based on the one or more determined production targets.

Abstract translation: 公开了一种用于在集成电路器件制造工艺的早期阶段提供容量比预测的方法。 该方法包括从一个或多个处理的晶片批次收集历史数据; 从一个或多个偏斜晶片批量收集测量数据; 从收集的历史数据和收集的测量数据生成估计的基线分布; 基于一个或多个指定参数和所生成的估计基线分布产生估计的性能分布; 通过对所生成的估计性能分布应用仓定义和产量退化因子估计来确定仓比预测; 根据仓比预测确定一个或多个生产目标; 以及基于所述一个或多个确定的生产目标来处理一个或多个晶圆。

公开(公告)号：US08041451B2

公开(公告)日：2011-10-18

申请号：US12427154

申请日：2009-04-21

Applicant: Sunny Wu ,  Chih-Sheng Shih ,  Andy Tsen ,  Jo Fei Wang ,  Jong-I Mou ,  Hsin Kuan

Inventor： Sunny Wu ,  Chih-Sheng Shih ,  Andy Tsen ,  Jo Fei Wang ,  Jong-I Mou ,  Hsin Kuan

IPC: G06F7/00 ,  G06F19/00 ,  G06F17/00 ,  G06Q10/00

CPC classification number: G05B19/41865 ,  G05B2219/32097 ,  G05B2219/32256 ,  G05B2219/32324 ,  G05B2219/45031 ,  G06Q10/087 ,  Y02P90/14 ,  Y02P90/20

Abstract: A method for providing bin-based control when manufacturing integrated circuit devices is disclosed. The method comprises performing a plurality of processes on a plurality of wafer lots; determining a required bin quantity, an actual bin quantity, and a projected bin quantity; comparing the determined required bin quantity with the determined actual bin quantity and determined projected bin quantity; and modifying at least one of the plurality of processes on the plurality of wafer lots if the determined actual bin quantity and determined projected bin quantity fail to satisfy the determined required bin quantity.

Abstract translation: 公开了一种在制造集成电路器件时提供基于bin的控制的方法。 该方法包括在多个晶片批次上执行多个处理; 确定所需的仓数量，实际箱数量和投影箱数量; 将确定的所需仓量与确定的实际箱数量和确定的预计仓量进行比较; 以及如果所确定的实际仓量和确定的投影箱数量不能满足所确定的所需仓量，则修改多个晶片批次上的多个处理中的至少一个。