Method for a bin ratio forecast at new tape out stage
    1.
    发明授权
    Method for a bin ratio forecast at new tape out stage 有权
    新磁带出站时的比例预测方法

    公开(公告)号:US08082055B2

    公开(公告)日:2011-12-20

    申请号:US12499345

    申请日:2009-07-08

    IPC分类号: G06F19/00

    CPC分类号: G06Q10/06 G06Q30/0202

    摘要: A method for providing a bin ratio forecast at an early stage of integrated circuit device manufacturing processes is disclosed. The method comprises collecting historical data from one or more processed wafer lots; collect measurement data from one or more skew wafer lots; generating an estimated baseline distribution from the collected historical data and collected measurement data; generating an estimated performance distribution based on one or more specified parameters and the generated estimated baseline distribution; determining a bin ratio forecast by applying a bin definition and a yield degradation factor estimation to the generated estimated performance distribution; determining one or more production targets based on the bin ratio forecast; and processing one or more wafers based on the one or more determined production targets.

    摘要翻译: 公开了一种用于在集成电路器件制造工艺的早期阶段提供容量比预测的方法。 该方法包括从一个或多个处理的晶片批次收集历史数据; 从一个或多个偏斜晶片批量收集测量数据; 从收集的历史数据和收集的测量数据生成估计的基线分布; 基于一个或多个指定参数和所生成的估计基线分布产生估计的性能分布; 通过对所生成的估计性能分布应用仓定义和产量退化因子估计来确定仓比预测; 根据仓比预测确定一个或多个生产目标; 以及基于所述一个或多个确定的生产目标来处理一个或多个晶圆。

    METHOD FOR A BIN RATIO FORECAST AT NEW TAPE OUT STAGE
    2.
    发明申请
    METHOD FOR A BIN RATIO FORECAST AT NEW TAPE OUT STAGE 有权
    新带前端的比率预测方法

    公开(公告)号:US20110010215A1

    公开(公告)日:2011-01-13

    申请号:US12499345

    申请日:2009-07-08

    IPC分类号: G06Q10/00 G06F17/18

    CPC分类号: G06Q10/06 G06Q30/0202

    摘要: A method for providing a bin ratio forecast at an early stage of integrated circuit device manufacturing processes is disclosed. The method comprises collecting historical data from one or more processed wafer lots; collect measurement data from one or more skew wafer lots; generating an estimated baseline distribution from the collected historical data and collected measurement data; generating an estimated performance distribution based on one or more specified parameters and the generated estimated baseline distribution; determining a bin ratio forecast by applying a bin definition and a yield degradation factor estimation to the generated estimated performance distribution; determining one or more production targets based on the bin ratio forecast; and processing one or more wafers based on the one or more determined production targets.

    摘要翻译: 公开了一种用于在集成电路器件制造工艺的早期阶段提供容量比预测的方法。 该方法包括从一个或多个处理的晶片批次收集历史数据; 从一个或多个偏斜晶片批量收集测量数据; 从收集的历史数据和收集的测量数据生成估计的基线分布; 基于一个或多个指定参数和所生成的估计基线分布产生估计的性能分布; 通过对所生成的估计性能分布应用仓定义和产量退化因子估计来确定仓比预测; 根据仓比预测确定一个或多个生产目标; 以及基于所述一个或多个确定的生产目标来处理一个或多个晶圆。

    Light emitting diode and manufacturing method thereof
    3.
    发明授权
    Light emitting diode and manufacturing method thereof 有权
    发光二极管及其制造方法

    公开(公告)号:US08946737B2

    公开(公告)日:2015-02-03

    申请号:US13570214

    申请日:2012-08-08

    IPC分类号: H01L33/00

    CPC分类号: H01L33/22 H01L33/007

    摘要: A light emitting diode (LED) includes a substrate, a buffer layer and an epitaxial structure. The substrate has a first surface with a patterning structure formed thereon. The patterning structure includes a plurality of projections. The buffer layer is arranged on the first surface of the substrate. The epitaxial structure is arranged on the buffer layer. The epitaxial structure includes a first semiconductor layer, an active layer and a second semiconductor layer arranged on the buffer layer in sequence. The first semiconductor layer has a second surface attached to the active layer. A distance between a peak of each the projections and the second surface of the first semiconductor layer is ranged from 0.5 μm to 2.5 μm.

    摘要翻译: 发光二极管(LED)包括衬底,缓冲层和外延结构。 衬底具有形成在其上的图案化结构的第一表面。 图案形成结构包括多个突起。 缓冲层布置在基板的第一表面上。 外延结构布置在缓冲层上。 外延结构包括顺序地布置在缓冲层上的第一半导体层,有源层和第二半导体层。 第一半导体层具有附着到有源层的第二表面。 每个突起的峰值与第一半导体层的第二表面之间的距离为0.5μm至2.5μm。

    Gallium nitride-based semiconductor device and method for manufacturing the same
    4.
    发明授权
    Gallium nitride-based semiconductor device and method for manufacturing the same 失效
    氮化镓基半导体器件及其制造方法

    公开(公告)号:US08349742B2

    公开(公告)日:2013-01-08

    申请号:US13013825

    申请日:2011-01-26

    IPC分类号: H01L21/00

    摘要: A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate.

    摘要翻译: 氮化镓系半导体器件包括复合衬底和氮化镓层。 复合衬底包括硅衬底和填料。 硅衬底包括第一表面和与第一表面相对的第二表面,并且第一表面在其中限定多个凹槽。 将填料填充到硅衬底的第一表面上的槽数中。 填料的热膨胀系数大于硅衬底的热膨胀系数。 氮化镓层形成在硅衬底的第二表面上。

    Tape roll in-series package machine
    5.
    发明授权
    Tape roll in-series package machine 失效
    卷筒式串联包装机

    公开(公告)号:US5732536A

    公开(公告)日:1998-03-31

    申请号:US739072

    申请日:1996-10-28

    IPC分类号: B65B5/10 B65B35/30

    CPC分类号: B65B5/106

    摘要: A tape roll in-series package machine for neatly packing a plurality of tape rolls into a paper box. In includes (a) a conveying device, (b) an in-series filling device, and (c) a paper box elevating device. The in-series filling device contains first, second, and third pneumatic cylinder each of which is connected to a receiving plate to cooperatively pack a row of the tape rolls into a paper box. The paper elevating device contains (i) a paper box conveyor which is divided into front section, middle and rear sections, each of the sections is driven by a separate mechanism; (ii) an elevating frame disposed above the middle section of the paper box conveyor, wherein the elevating frame contains a pair of fending plates each being driven by a revolving pneumatic cylinder for holding the paper box in place and facilitating the incoming and outgoing motions of the paper box; and (iii) a Z-axis stepping motor which is provided to control an up-and-down motion of the elevating frame so as to adjust a vertical position of the paper box.

    摘要翻译: 一种用于将多个带卷整齐地包装在纸盒中的胶带卷筒式包装机。 包括(a)输送装置,(b)串联充填装置,和(c)纸盒升降装置。 串联式灌装装置包括第一,第二和第三气缸,每个气缸连接到接收板,以将一排带卷协同地包装在纸盒中。 纸张升降装置包括:(i)纸箱输送机,其分为前段,中间和后段,每个区段由单独的机构驱动; (ii)设置在纸箱输送机的中间部分上方的升降框架,其中升降架包括一对防火板,每个挡板由用于将纸盒保持在适当位置的旋转气动缸驱动,并且有利于进入和离开运动 纸盒; 和(iii)Z轴步进电机,其被设置为控制升降框架的上下运动,以调节纸盒的垂直位置。

    Light emitting diode chip and method of manufacturing the same
    9.
    发明授权
    Light emitting diode chip and method of manufacturing the same 失效
    发光二极管芯片及其制造方法

    公开(公告)号:US08461619B2

    公开(公告)日:2013-06-11

    申请号:US13397688

    申请日:2012-02-16

    IPC分类号: H01L33/36

    摘要: An LED chip includes a substrate, a first type semiconductor layer, a light-emitting layer, a second type semiconductor layer, a first electrode and a second electrode formed on the substrate in sequence. A surface of the first type semiconductor layer away from the substrate comprises an exposed first area and a second area covered by the light-emitting layer. The first electrode is formed on the exposed first area of the substrate. A number of recesses are defined in the second area of the surface of the first type semiconductor layer. The recesses are spaced apart from each other and arranged in sequence in a direction away from the first electrode; depths of the recesses gradually decrease following an increase of a distance between the recesses and the first electrode. The second electrode is formed on the second type semiconductor layer.

    摘要翻译: LED芯片依次包括基板,第一类型半导体层,发光层,第二类型半导体层,第一电极和第二电极。 离开衬底的第一类型半导体层的表面包括暴露的第一区域和被发光层覆盖的第二区域。 第一电极形成在基板的暴露的第一区域上。 在第一类型半导体层的表面的第二区域中限定多个凹部。 凹部彼此间隔开并且沿远离第一电极的方向依次布置; 随着凹部和第一电极之间的距离的增加,凹部的深度逐渐减小。 第二电极形成在第二类型半导体层上。