公开(公告)号：US08357593B2

公开(公告)日：2013-01-22

申请号：US12688044

申请日：2010-01-15

Applicant: Ki-chul Kim ,  Youn-soo Kim ,  Ki-vin Im ,  Cha-young Yoo ,  Jong-cheol Lee ,  Ki-yeon Park ,  Hoon-sang Choi ,  Se-hoon Oh

Inventor： Ki-chul Kim ,  Youn-soo Kim ,  Ki-vin Im ,  Cha-young Yoo ,  Jong-cheol Lee ,  Ki-yeon Park ,  Hoon-sang Choi ,  Se-hoon Oh

IPC: H01L21/322

CPC classification number: H01L21/314 ,  H01L21/02041 ,  H01L21/67034

Abstract: Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate.

Abstract translation: 提供了除去吸附或结合到半导体衬底的表面的水的方法，以及使用本文所述除去水的方法沉积原子层的方法。 除去水的方法包括向半导体衬底的表面施加化学溶剂，并从半导体衬底的表面除去化学溶剂。

公开(公告)号：US20100190320A1

公开(公告)日：2010-07-29

申请号：US12688044

申请日：2010-01-15

Applicant: Ki-chul Kim ,  Youn-soo Kim ,  Ki-vin Im ,  Cha-young Yoo ,  Jong-cheol Lee ,  Ki-yeon Park ,  Hoon-sang Choi ,  Se-hoon Oh

Inventor： Ki-chul Kim ,  Youn-soo Kim ,  Ki-vin Im ,  Cha-young Yoo ,  Jong-cheol Lee ,  Ki-yeon Park ,  Hoon-sang Choi ,  Se-hoon Oh

IPC: H01L21/30 ,  B08B3/00

CPC classification number: H01L21/314 ,  H01L21/02041 ,  H01L21/67034

Abstract: Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate.

Abstract translation: 提供了除去吸附或结合到半导体衬底的表面的水的方法，以及使用本文所述除去水的方法沉积原子层的方法。 除去水的方法包括向半导体衬底的表面施加化学溶剂，并从半导体衬底的表面除去化学溶剂。

公开(公告)号：US20100072536A1

公开(公告)日：2010-03-25

申请号：US12591109

申请日：2009-11-09

Applicant: Se-Hoon Ho ,  Yong-Geun Park ,  Han-Mel Choi ,  Seung-Hwan Lee ,  Ki-Yeon Park ,  Sun-Jung Kim

Inventor： Se-Hoon Ho ,  Yong-Geun Park ,  Han-Mel Choi ,  Seung-Hwan Lee ,  Ki-Yeon Park ,  Sun-Jung Kim

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/513

Abstract: In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

Abstract translation: 在非易失性存储器件和制造非易失性存储器件的方法中，隧道绝缘层，电荷俘获层，电介质层和导电层可以顺序形成在衬底的沟道区上。 可以将导电层图案化以形成栅电极，并且可以在栅电极的侧壁上形成间隔物。 可以通过使用间隔物作为蚀刻掩模的各向异性蚀刻工艺在沟道区上形成电介质层图案，电荷俘获层图案和隧道绝缘层图案。 可以通过各向同性蚀刻工艺去除电荷俘获层图案的侧壁以减小其宽度。 因此，电荷捕获层图案中电子的横向扩散的可能性可能会降低或被抑制，并且可以提高非易失性存储器件的高温应力特性。

公开(公告)号：US07635633B2

公开(公告)日：2009-12-22

申请号：US11898039

申请日：2007-09-07

Applicant: Se-Hoon Oh ,  Young-Geun Park ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Ki-Yeon Park ,  Sun-Jung Kim

Inventor： Se-Hoon Oh ,  Young-Geun Park ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Ki-Yeon Park ,  Sun-Jung Kim

IPC: H01L21/336

CPC classification number: H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

Abstract: In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

Abstract translation: 在非易失性存储器件和制造非易失性存储器件的方法中，隧道绝缘层，电荷俘获层，电介质层和导电层可以顺序形成在衬底的沟道区上。 可以将导电层图案化以形成栅电极，并且可以在栅电极的侧壁上形成间隔物。 可以通过使用间隔物作为蚀刻掩模的各向异性蚀刻工艺在沟道区上形成电介质层图案，电荷俘获层图案和隧道绝缘层图案。 可以通过各向同性蚀刻工艺去除电荷俘获层图案的侧壁以减小其宽度。 因此，电荷捕获层图案中电子的横向扩散的可能性可能会降低或被抑制，并且可以提高非易失性存储器件的高温应力特性。

公开(公告)号：US07605067B2

公开(公告)日：2009-10-20

申请号：US11859618

申请日：2007-09-21

Applicant: Ki-Yeon Park ,  Sun-Jung Kim ,  Min-Kyung Ryu ,  Seung-Hwan Lee ,  Han-Mei Choi

Inventor： Ki-Yeon Park ,  Sun-Jung Kim ,  Min-Kyung Ryu ,  Seung-Hwan Lee ,  Han-Mei Choi

IPC: H01L21/3205

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: A method of manufacturing a non-volatile memory device includes forming a tunnel insulating layer on a substrate, forming a conductive pattern on the tunnel insulating layer, forming a lower dielectric layer on the conductive pattern, performing a first heat treatment process to density the lower dielectric layer, and forming a middle dielectric layer having an energy band gap smaller than that of the lower dielectric layer on the first heat-treated lower dielectric layer. The method further includes forming an upper dielectric layer including a material substantially identical to that of the lower dielectric layer on the middle dielectric layer, performing a second heat treatment process to densify the middle dielectric layer and the upper dielectric layer and forming a conductive layer on the second heat-treated upper dielectric layer.

Abstract translation: 一种制造非易失性存储器件的方法包括在衬底上形成隧道绝缘层，在隧道绝缘层上形成导电图案，在导电图案上形成下介电层，执行第一热处理工艺以密度较低 并且形成具有比第一经热处理的下电介质层上的下介电层的能带隙小的能带隙的中间电介质层。 该方法还包括形成上介电层，其包括与中间介电层上的下电介质层的材料基本相同的材料，执行第二热处理工艺以使中介电层和上电介质层致密并形成导电层 第二热处理的上介电层。

公开(公告)号：US20080096349A1

公开(公告)日：2008-04-24

申请号：US11605452

申请日：2006-11-29

Applicant: Ki-yeon Park ,  Han-mei Choi ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim

Inventor： Ki-yeon Park ,  Han-mei Choi ,  Seung-hwan Lee ,  Sung-tae Kim ,  Young-sun Kim

IPC: H01L21/336

CPC classification number: H01L29/792 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/3143 ,  H01L21/31604 ,  H01L21/3162 ,  H01L29/513 ,  H01L29/66833

Abstract: A method of fabricating a nonvolatile memory device includes forming a charge tunneling layer on a semiconductor substrate, forming a charge trapping layer on the charge tunneling layer, forming a first charge blocking layer on the charge trapping layer by supplying a metal source gas and a first oxidizing gas onto the charge trapping layer, forming a second charge blocking layer on the first charge blocking layer by supplying a metal source gas and a second oxidizing gas onto the first charge blocking layer, wherein the second oxidizing gas has a higher oxidizing power as compared to the first oxidizing gas, and forming a gate electrode layer on the second charge blocking layer.

Abstract translation: 一种制造非易失性存储器件的方法包括：在半导体衬底上形成电荷隧穿层，在电荷隧道层上形成电荷俘获层，在电荷俘获层上形成第一电荷阻挡层，通过提供金属源气体和第一 在电荷捕获层上氧化气体，通过在第一电荷阻挡层上提供金属源气体和第二氧化气体，在第一电荷阻挡层上形成第二电荷阻挡层，其中第二氧化气体具有较高的氧化能力， 并且在第二电荷阻挡层上形成栅极电极层。

公开(公告)号：US20060072281A1

公开(公告)日：2006-04-06

申请号：US11196943

申请日：2005-08-04

Applicant: Gab-Jin Nam ,  Young-Geun Park ,  Young-Sun Kim ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Ki-Yeon Park ,  Cha-Young You

Inventor： Gab-Jin Nam ,  Young-Geun Park ,  Young-Sun Kim ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Ki-Yeon Park ,  Cha-Young You

IPC: H01G4/06

CPC classification number: H01L21/02192 ,  C23C16/40 ,  H01G4/105 ,  H01G4/1272 ,  H01G4/33 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L23/5223 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention can provide methods of forming a layer including lanthanum by utilizing a lanthanum precursor existing in a liquid phase at a room temperature. The present invention can further provide methods of forming layers including lanthanum on objects and methods of manufacturing a capacitor.

Abstract translation: 本发明可以提供通过利用在室温下存在于液相中的镧前体形成包含镧的层的方法。 本发明还可以提供形成包括镧在内的层的方法和制造电容器的方法。

公开(公告)号：US20050272272A1

公开(公告)日：2005-12-08

申请号：US11198541

申请日：2005-08-05

Applicant: Jae-Hyun Yeo ,  Sung-Tae Kim ,  Young-Sun Kim ,  In-Sung Park ,  Seok-Jun Won ,  Yun-Jung Lee ,  Ki-Vin Im ,  Ki-Yeon Park

Inventor： Jae-Hyun Yeo ,  Sung-Tae Kim ,  Young-Sun Kim ,  In-Sung Park ,  Seok-Jun Won ,  Yun-Jung Lee ,  Ki-Vin Im ,  Ki-Yeon Park

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/469 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/02271 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/0234 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L28/40

Abstract: A semiconductor device and a method for forming the same. A dielectric layer is formed on a semiconductor substrate or on a lower electrode of a capacitor. Vacuum annealing is performed on the dielectric layer. Thus, impurities remaining in the dielectric layer can be effectively removed, and the dielectric layer can be densified. As a result, the electrical characteristics of the semiconductor device are improved. For example, the leakage current characteristics of the dielectric layer are improved and capacitance is increased.

Abstract translation: 一种半导体器件及其形成方法。 电介质层形成在半导体衬底上或电容器的下电极上。 在电介质层上进行真空退火。 因此，可以有效地除去残留在电介质层中的杂质，并且可以使电介质层致密化。 结果，提高了半导体器件的电特性。 例如，介电层的漏电流特性得到改善，电容增大。

公开(公告)号：US20050170601A1

公开(公告)日：2005-08-04

申请号：US11059449

申请日：2005-02-17

Applicant: Kyoung-Ryul Yoon ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Dae-Sik Choi ,  Ki-Yeon Park ,  Young-Sun Kim ,  Sung-Tae Kim ,  Cha-Young You

Inventor： Kyoung-Ryul Yoon ,  Han-Mei Choi ,  Seung-Hwan Lee ,  Dae-Sik Choi ,  Ki-Yeon Park ,  Young-Sun Kim ,  Sung-Tae Kim ,  Cha-Young You

IPC: H01L21/20 ,  H01L29/04 ,  H01L29/10 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC classification number: H01L28/40 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/022 ,  H01L21/0228 ,  H01L27/1085 ,  H01L28/65 ,  H01L28/90

Abstract: A capacitor including a dielectric structure, a lower electrode may be formed on a substrate. The dielectric structure may be formed on the lower electrode, and may include a first thin film, which may improve a morphology of the dielectric structure, and a second thin film, which may have at least one of an EOT larger than that of the first thin film and a dielectric constant higher than that of the first thin film. An upper electrode may be formed on the dielectric structure, and the dielectric structure may have an improved morphology and/or a higher dielectric constant.

Abstract translation: 可以在基板上形成包括电介质结构的电容器，下部电极。 电介质结构可以形成在下电极上，并且可以包括可以改善电介质结构的形态的第一薄膜和可以具有大于第一薄膜的EOT中的至少一个的第二薄膜 薄膜和比第一薄膜高的介电常数。 可以在电介质结构上形成上电极，并且电介质结构可以具有改进的形态和/或更高的介电常数。

公开(公告)号：US20050051828A1

公开(公告)日：2005-03-10

申请号：US10828596

申请日：2004-04-21

Applicant: Ki-yeon Park ,  Sung-tae Kim ,  Young-sun Kim ,  In-sung Park ,  Jae-hyun Yeo ,  Yun-jung Lee ,  Ki-vin Im

Inventor： Ki-yeon Park ,  Sung-tae Kim ,  Young-sun Kim ,  In-sung Park ,  Jae-hyun Yeo ,  Yun-jung Lee ,  Ki-vin Im

IPC: H01L21/20 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242 ,  H01B1/00 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119 ,  H01L21/31

CPC classification number: H01L21/0228 ,  C23C16/40 ,  C23C16/45529 ,  C23C16/45553 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02337 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/1085

Abstract: The present invention provides methods of forming metal thin films, lanthanum oxide films and high dielectric films. Compositions of metal thin films, lanthanum oxide films and high dielectric films are also provided. Further provided are semiconductor devices comprising the metal thin films, lanthanum oxide films and high dielectric films provided herein.

Abstract translation: 本发明提供形成金属薄膜，氧化镧膜和高介电膜的方法。 还提供了金属薄膜，氧化镧薄膜和高介电薄膜的组成。 还提供了包括金属薄膜，氧化镧膜和本文提供的高介电膜的半导体器件。