公开(公告)号：US06459123B1

公开(公告)日：2002-10-01

申请号：US09302768

申请日：1999-04-30

Applicant: Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

Inventor： Gerhard Enders ,  Thomas Schulz ,  Dietrich Widmann ,  Lothar Risch

IPC: H01L2994

CPC classification number: H01L27/11 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1203

Abstract: A semiconductor body having a pair of vertical, double-gated CMOS transistors. An insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors. The transistors, together with additional such transistors, are arranged to form a Synchronous Dynamic Random Access Memory (SRAM) array. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORLDINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells. One of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells. Each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.

Abstract translation: 具有一对垂直双门控CMOS晶体管的半导体本体。 在半导体本体的表面下水平延伸的绝缘层，该绝缘层设置在该对晶体管的下方。 晶体管与附加的这种晶体管一起被布置成形成同步动态随机存取存储器（SRAM）阵列。 阵列包括以行和列排列的多个SRAM单元，每个单元都具有连接到WORLDINE CONTACT的WORDLINE。 WORDLINE CONTACT是四个连续的一个单元格共同的。 具有多个电互连的MOS晶体管的单元之一被布置成提供SRAM电路。 每个单元都有一个VDD CONTACT和一个VSS CONTACT。 这种CONTACT之一被布置在每个单元格的中心并且另一个CONTACT被四个相邻的单元共同。 每个单元格具有共同的一个CONTACT和WORDLINE CONTACT放置在单元的外围角区域。

公开(公告)号：US06320447B1

公开(公告)日：2001-11-20

申请号：US09707032

申请日：2000-11-06

Applicant: Wolfgang Rösner ,  Ties Ramcke ,  Lothar Risch

Inventor： Wolfgang Rösner ,  Ties Ramcke ,  Lothar Risch

IPC: H03K1762

CPC classification number: G06F7/527 ,  B82Y10/00 ,  G06F7/502 ,  G06F7/505 ,  G06F2207/4828 ,  H03K19/08 ,  Y10S977/936 ,  Y10S977/937 ,  Y10S977/94

Abstract: The circuit configuration has at least five single-electron transistors, three of which are connected via a second main node and a third main node between a first main node and an output. The fourth single-electron transistor is connected between the second main node and a first supply voltage, with its gate electrode being connected to the first main node. The fifth single-electron transistor is connected between the third main node and the first supply voltage, with its gate electrode being connected to the second main node. The circuit configuration is suitable for use as a full adder and as a multiplier.

Abstract translation: 电路配置具有至少五个单电子晶体管，其中三个通过第二主节点和第一主节点与输出端之间的第三主节点连接。 第四单电子晶体管连接在第二主节点和第一电源电压之间，其栅电极连接到第一主节点。 第五单电晶体管连接在第三主节点和第一电源电压之间，其栅电极连接到第二主节点。 电路配置适合用作全加器和乘法器。

公开(公告)号：US06307422B1

公开(公告)日：2001-10-23

申请号：US09516658

申请日：2000-03-01

Applicant: Wolfgang Roesner ,  Ties Ramcke ,  Lothar Risch

Inventor： Wolfgang Roesner ,  Ties Ramcke ,  Lothar Risch

IPC: H03K17687

CPC classification number: G06F7/505 ,  G06F7/502 ,  G06F2207/4828 ,  H03K19/02 ,  Y10S977/89 ,  Y10S977/937 ,  Y10S977/94

Abstract: At least one single-electron transistor is provided in a circuit configuration having single-electron components, and is connected between a first main node and a second main node. The first main node is capacitively connected between a first operating voltage connection and a second operating voltage connection. The gate electrode of the single-electron transistor is connected to a control voltage connection. The circuit configuration is suitable for logic operations on binary numbers, whose digits are stored at the first and second main nodes.

Abstract translation: 至少一个单电子晶体管以具有单电子分量的电路配置提供，并且连接在第一主节点和第二主节点之间。 第一主节点电容连接在第一工作电压连接和第二工作电压连接之间。 单电子晶体管的栅电极连接到控制电压连接。 电路配置适用于二进制数字的逻辑运算，其数字存储在第一和第二主节点。

公开(公告)号：US06274431B1

公开(公告)日：2001-08-14

申请号：US09301108

申请日：1999-04-28

Applicant: Lothar Risch ,  Wolfgang Roesner ,  Thomas Aeugle ,  Wolfgang Krautschneider

Inventor： Lothar Risch ,  Wolfgang Roesner ,  Thomas Aeugle ,  Wolfgang Krautschneider

IPC: H01L2976

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1037 ,  H01L29/4236 ,  H01L29/66666

Abstract: An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

Abstract translation: 集成电路装置包含由绝缘结构围绕的MOS晶体管，其源极和漏极横向排列并且在不同的深度。 其通道基本上垂直于电路装置的表面。 由于通过蚀刻或通过生长层来确定沟道长度，所以可以实现短于小于50nm的沟道长度。 为了制造，采用其中集成平面晶体管的传统电路布置的大多数掩模，这显着地有助于结合到半导体制造中。

公开(公告)号：US06229169B1

公开(公告)日：2001-05-08

申请号：US09213724

申请日：1998-12-17

Applicant: Franz Hofmann ,  Wolfgang Krautschneider ,  Wolfgang Rösner ,  Lothar Risch ,  Till Schlösser ,  Paul-Werner Basse

Inventor： Franz Hofmann ,  Wolfgang Krautschneider ,  Wolfgang Rösner ,  Lothar Risch ,  Till Schlösser ,  Paul-Werner Basse

IPC: H01L27108

CPC classification number: H01L27/11502 ,  H01L27/108 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11507

Abstract: A memory cell configuration contains a multiplicity of memory cells in a semiconductor substrate. Each of the memory cells has a selection transistor connected between a bit line and a storage element. The memory cells can each be driven via a first word line and a second word line, the first word line and the second word line crossing one another. The memory cell configuration is, in particular, a DRAM configuration.

Abstract translation: 存储单元配置在半导体衬底中包含多个存储单元。 每个存储单元具有连接在位线和存储元件之间的选择晶体管。 每个存储器单元可以通过第一字线和第二字线驱动，第一字线和第二字线彼此交叉。 存储单元配置尤其是DRAM配置。

公开(公告)号：US6066876A

公开(公告)日：2000-05-23

申请号：US65173

申请日：1998-04-23

Applicant: Lothar Risch ,  Wolfgang Roesner ,  Thomas Aeugle ,  Wolfgang Krautschneider

Inventor： Lothar Risch ,  Wolfgang Roesner ,  Thomas Aeugle ,  Wolfgang Krautschneider

IPC: H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/4236

Abstract: An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

Abstract translation: 集成电路装置包含由绝缘结构包围的MOS晶体管，其源极和漏极横向设置在不同的深度。 其通道基本上垂直于电路装置的表面。 由于通过蚀刻或通过生长层来确定沟道长度，所以可以实现短于小于50nm的沟道长度。 为了制造，采用其中集成平面晶体管的传统电路布置的大多数掩模，这显着地有助于结合到半导体制造中。

公开(公告)号：US5920778A

公开(公告)日：1999-07-06

申请号：US913740

申请日：1997-09-23

Applicant: Wolfgang Rosner ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Lothar Risch

Inventor： Wolfgang Rosner ,  Wolfgang Krautschneider ,  Franz Hofmann ,  Lothar Risch

IPC: H01L21/8246 ,  H01L27/112

CPC classification number: H01L27/11273 ,  H01L27/112

Abstract: In a read-only memory cell arrangement having first memory cells which contain a vertical MOS transistor, and having second memory cells which do not contain vertical MOS transistors, the memory cells are arranged along opposite flanks of strip-shaped parallel insulation trenches (16). The width of the insulation trenches (16) is preferably equal to their separation, so that the memory cell arrangement can be produced with a space requirement of 2F.sup.2 per memory cell, F being the minimum structure size in the respective technology.

Abstract translation: PCT No.PCT / DE96 / 00614 Sec。 371日期1997年9月23日 102（e）1997年9月23日PCT PCT 1996年4月9日PCT公布。 公开号WO96 / 3351300 日期1996年10月24日在具有包含垂直MOS晶体管的第一存储单元且具有不包含垂直MOS晶体管的第二存储单元的只读存储单元布置中，存储单元沿着带状平行的相对侧布置 绝缘沟槽（16）。 绝缘沟槽（16）的宽度优选等于它们的间隔，使得可以以每个存储单元的空间要求为2F2来生产存储单元布置，F是相应技术中的最小结构尺寸。

公开(公告)号：US5559353A

公开(公告)日：1996-09-24

申请号：US332737

申请日：1994-11-01

Applicant: Lothar Risch ,  Thomas Vogelsang ,  Franz Hofmann ,  Karl Hofmann

Inventor： Lothar Risch ,  Thomas Vogelsang ,  Franz Hofmann ,  Karl Hofmann

IPC: H01L21/8238 ,  H01L21/762 ,  H01L27/092 ,  H03K19/0948 ,  H01L29/78

CPC classification number: H03K19/0948 ,  H01L21/76294 ,  H01L27/0922

Abstract: A first MOS transistor and a second MOS transistor are connected in series with a first complementary MOS transistor and a second complementary MOS transistor that are connected in parallel with one another. The transistors are each realized as a vertical layer sequence that forms the source, channel and drain and that which has a sidewall at which a gate dielectric and a gate electrode are arranged. The complementary MOS transistors connected in parallel with one another are realized in a common layer sequence of the source, channel and drain. The layer sequences that form the series-connected transistors are arranged above one another. The circuit structure is manufactured by epitaxal definition of the layer sequences, such as by molecular beam epitaxy.

Abstract translation: 第一MOS晶体管和第二MOS晶体管与彼此并联连接的第一互补MOS晶体管和第二互补MOS晶体管串联连接。 晶体管各自被实现为形成源极，沟道和漏极的垂直层序列，并且其具有设置栅极电介质和栅电极的侧壁。 在源极，沟道和漏极的公共层序列中实现彼此并联连接的互补MOS晶体管。 形成串联晶体管的层序列彼此重叠。 电路结构通过层序列的上层定义（例如通过分子束外延）来制造。

公开(公告)号：US5327374A

公开(公告)日：1994-07-05

申请号：US956896

申请日：1992-12-29

Applicant: Wolfgang Krautschneider ,  Klaus Lau ,  Lothar Risch

Inventor： Wolfgang Krautschneider ,  Klaus Lau ,  Lothar Risch

IPC: H01L27/10 ,  G11C5/00 ,  G11C11/402 ,  G11C11/404 ,  G11C11/405 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/06 ,  G11C7/00

CPC classification number: G11C11/405 ,  G11C11/404 ,  G11C5/005 ,  H01L27/108

Abstract: An arrangement with self-amplifying dynamic MOS transistor storage cells has in each case a MOS selection transistor AT, whose gate is connected to a word line WL, and an MOS storage transistor ST at whose gate a capacitor C for charge storage acts. This self-amplifying storage cell can be written on and read out with only one bit line BL and one word line WL. The two transistors AT and ST are connected in series and a common drain source region DS is connected via a voltage-dependent resistor VR to the gate electrode GST of the control transistor. The advantages reside in the fact that the cell geometry can be scaled without at the same time the quantity Q of charge which can be read out on the bit line BL having to be reduced, in that the quantity Q of charge which can be read out is larger than a charge stored in the capacitor C which acts at the gate of the storage transistor ST and in that the two MOS transistors AT and ST can be produced relatively simply.

Abstract translation: PCT No.PCT / DE91 / 00502 Sec。 371日期1992年12月29日 102（e）1992年12月29日PCT PCT 1991年7月18日PCT公布。 公开号WO92 / 01287 日本1992年1月23日。具有自放大动态MOS晶体管存储单元的布置在每种情况下都是MOS选择晶体管AT，其栅极连接到字线WL，MOS存储晶体管ST在其栅极处具有电容器C 用于充电存储动作。 该自放大存储单元可以仅用一个位线BL和一个字线WL写入和读出。 两个晶体管AT和ST串联连接，并且公共漏极源极区域DS经由电压依赖电阻器VR连接到控制晶体管的栅电极GST。 优点在于，可以对单元几何形状进行缩放，而不必同时在位线BL上读出的电荷量Q必须减小，因为可以读出的电荷量Q 大于存储在存储晶体管ST的栅极处的电容器C中存储的电荷，并且可以相对简单地制造两个MOS晶体管AT和ST。

公开(公告)号：US4331709A

公开(公告)日：1982-05-25

申请号：US171180

申请日：1980-07-22

Applicant: Lothar Risch ,  Erich Pammer ,  Karlheinz Friedrich

Inventor： Lothar Risch ,  Erich Pammer ,  Karlheinz Friedrich

IPC: H01L21/336 ,  H01L21/28 ,  H01L21/314 ,  H01L21/318 ,  H01L21/324 ,  H01L21/339 ,  H01L23/29 ,  H01L29/51 ,  H01L29/76 ,  H01L29/762 ,  H01L29/772 ,  H01L29/78

CPC classification number: H01L21/28185 ,  H01L21/28176 ,  H01L21/314 ,  H01L21/3185 ,  H01L21/324 ,  H01L23/291 ,  H01L23/298 ,  H01L29/518 ,  H01L21/28194 ,  H01L2924/0002 ,  Y10S438/91

Abstract: Fast surface states in MOS devices, such as SCCDs, are reduced by depositing a relatively thin amorphous layer containing silicon and hydrogen onto the SiO.sub.2 surface of such devices and annealing the resultant device in a non-oxidizing atmosphere for brief periods of time at a temperature in excess of the deposition temperature for the amorphous layer but below about 500.degree. C. so that free valences at the Si-SiO.sub.2 interface region are saturated with hydrogen. Surface state densities of about 4.times.10.sup.8 cm.sup.-2 eV.sup.-1 and SCCDs having .epsilon.=1.10.sup.-5 can be achieved via this process. The process is useful in producing SCCDs with low surface state densities and other MOS devices having low surface generated dark currents.

Abstract translation: 通过在这样的器件的SiO 2表面上沉积含有硅和氢的相对薄的无定形层，并在非氧化性气氛中在温度下短时间内退火所得到的器件，减少MOS器件（例如SCCD）中的快速表面状态 超过非晶层的沉积温度但低于约500℃，使得Si-SiO 2界面区域处的自由价态被氢饱和。 约4×10 8 cm -2eV-1的表面状态密度和ε= 1.10-5的SCCD可以通过该方法实现。 该方法可用于生产具有低表面状态密度的SCCD和具有低表面产生暗电流的其它MOS器件。