公开(公告)号：US20050141291A1

公开(公告)日：2005-06-30

申请号：US11068228

申请日：2005-03-01

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Yasuhiko Matsunaga

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/26 ,  G11C16/0483 ,  H01L27/115

摘要： A semiconductor memory including a memory cell unit, the memory cell unit comprising: a plurality of memory cells in which each conductance between current terminals changes according to held data, each having a plurality of current terminals connected in series between a first terminal and a second terminal, and each capable of electrically rewriting the data; a first select switching element electrically connecting said first terminal to a data transfer line; and a MISFET serving as a second select switching element connecting said second terminal to a reference potential line, wherein said semiconductor memory has a data read mode for forcing the first and second select switching elements of said memory cell unit into conduction, applying a read voltage for forcing a path between the current terminals into conduction or cut-off according to the data of a selected memory cell, to a control electrode of the selected memory cell, applying a pass voltage for forcing a path between the current terminals into conduction irrespectively of the data of each of the memory cells other than said selected memory cell, to the control electrode of each of the memory cells other than said selected memory cell, and detecting presence and absence or magnitude of a current between said data transfer line and said reference potential line, and in said data read mode, a conductance between current terminals of said MISFET is set lower than a conductance, in the case where the conductance between the current terminals is set to be the lowest, with regards to at least one of the memory cells other than said selected memory cell.

公开(公告)号：US20050133874A1

公开(公告)日：2005-06-23

申请号：US11007462

申请日：2004-12-09

申请人： Akira Goda ,  Mitsuhiro Noguchi ,  Yuji Takeuchi ,  Michiharu Matsui ,  Hiroaki Hazama

发明人： Akira Goda ,  Mitsuhiro Noguchi ,  Yuji Takeuchi ,  Michiharu Matsui ,  Hiroaki Hazama

IPC分类号： H01L27/115 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/76232 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11573

摘要： The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode are formed in the first region. A second gate insulating film different from the first gate insulating film and a second gate electrode are formed in the second region. A device isolation region is formed in the boundary area. This device isolation region includes a trench formed in the major surface, and an insulating layer having a portion buried in the trench and a portion projecting upward from the major surface. The bottom of the trench has depths different with portions.

摘要翻译： 半导体器件的半导体衬底的主表面包括第一和第二区域以及它们之间的边界区域。 第一栅极绝缘膜和第一栅电极形成在第一区域中。 在第二区域中形成与第一栅极绝缘膜和第二栅极电极不同的第二栅极绝缘膜。 在边界区域形成器件隔离区。 该器件隔离区域包括形成在主表面中的沟槽，以及绝缘层，其具有埋在沟槽中的部分和从主表面向上突出的部分。 沟槽的底部具有与部分不同的深度。

公开(公告)号：US20050128843A1

公开(公告)日：2005-06-16

申请号：US10983617

申请日：2004-11-09

申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Hiroshi Maejima ,  Takahiko Hara

发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Hiroshi Maejima ,  Takahiko Hara

IPC分类号： H01L21/3205 ,  H01L21/8247 ,  H01L23/52 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/7881 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.

摘要翻译： 根据本发明的非易失性半导体存储器包括：存储单元单元，其包括彼此并联形成的数据选择线，与数据选择线相交并且彼此并联排列的数据传输线;以及电可重写存储单元晶体管， 数据传输线和数据选择线的交点。 它还包括：存储单元阵列块，其中存储单元单元沿数据选择线设置; 第一源极线，连接到存储单元单元的一端，并沿数据选择线对齐; 以及第二源极线，其电连接到第一源极线，并且沿着数据选择线布置。

公开(公告)号：US06882592B2

公开(公告)日：2005-04-19

申请号：US10696028

申请日：2003-10-30

申请人： Mitsuhiro Noguchi ,  Akira Goda ,  Hiroyuki Nitta

发明人： Mitsuhiro Noguchi ,  Akira Goda ,  Hiroyuki Nitta

IPC分类号： G11C16/02 ,  G06F11/10 ,  G11C8/00 ,  G11C11/34 ,  G11C16/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C29/42 ,  G11C29/52 ,  H01L21/8247 ,  H01L27/00 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G06F11/1008 ,  G06F11/108 ,  G11C7/22 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3454 ,  G11C29/50004 ,  G11C29/52 ,  G11C29/76 ,  G11C29/82 ,  G11C29/84 ,  G11C2029/0409 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device includes: a memory cell array having a plurality of data select lines disposed in parallel with each other, a plurality of data transfer line disposed in parallel with each other to intersect the data select lines, and electrically rewritable memory cells laid out at cross portions between the data select lines and data transfer lines; a data select line driver for driving the data select lines of the memory cell array; a sense amplifier circuit connected to the data transfer lines of the memory cell array, for performing data read of memory cells selected by one of the data select lines; and a control circuit used for timing control of data read of the memory cell array, for outputting at least two types of timing signals as being different in accordance with a selected data area of the memory cell array.

公开(公告)号：US06774462B2

公开(公告)日：2004-08-10

申请号：US10278882

申请日：2002-10-24

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

IPC分类号： H01L2358

CPC分类号： H01L21/022 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/76838 ,  H01L21/76897 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/792

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜， 包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在 下氮化硅膜比上述氮化硅膜高。

公开(公告)号：US06773225B2

公开(公告)日：2004-08-10

申请号：US10156922

申请日：2002-05-30

申请人： Masanori Yuri ,  Vincent Laurello ,  Charles Ellis ,  Mitsuhiro Noguchi ,  Keita Fujii

发明人： Masanori Yuri ,  Vincent Laurello ,  Charles Ellis ,  Mitsuhiro Noguchi ,  Keita Fujii

IPC分类号： F01D518

CPC分类号： F01D5/08 ,  F01D11/005 ,  F01D11/02

摘要： In order to provide a gas turbine and a gas bleeding method which can prevent the loss of drive power due to gas bleeding to the rotor disk, bleed gas is imparted with swirling flow in the same rotational direction as that of a first stage rotor disk by being passed through a set of TOBI nozzles which constitute a flow conduit therefor, and is supplied to this first stage rotor disk, with a portion of this bleed gas flow being bypassed and being supplied between first stage stationary blades and first stage moving blades.

摘要翻译： 为了提供一种能够防止由于气体向转子盘流出而引起的驱动力的损失的燃气轮机和排气方式，排出气体与第一级转子盘的旋转方向相同地旋转， 通过一组构成其流动管道的TOBI喷嘴，并且被供应到该第一级转子盘，该排出气体流的一部分被旁路并被供应在第一级固定叶片和第一级动叶片之间。

公开(公告)号：US06504237B2

公开(公告)日：2003-01-07

申请号：US10188752

申请日：2002-07-05

申请人： Mitsuhiro Noguchi ,  Akira Nishiyama

发明人： Mitsuhiro Noguchi ,  Akira Nishiyama

IPC分类号： H01L23495

CPC分类号： H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical wiring structure capable of improving a wiring delay to thereby achieve both low power consumption and high-speed performances without accompanying any significant changes in circuit layout and wiring structure of prior known CMOS logic circuitry and also alterations of the multilayer configuration of wiring layers is provided. A local wiring 1 and global wirings 2, 3 are stacked over a semiconductor substrate 10 in this order of sequence when looked at from lower part in a lamination direction, with dielectric layers sandwiched between adjacent ones of these layers. A distance between the local wiring 1 and the global wiring 2 is so formed as to be greater than a distance between the global wiring layer 2 and the global wiring, 3. Thus provided is a semiconductor device featured in that a drive voltage used to drive the global wirings 2, 3 is potentially lower than a drive voltage for driving inside of the local wiring 1.

摘要翻译： 一种能够改善布线延迟从而实现低功耗和高速性能的电布线结构，而不伴随现有已知CMOS逻辑电路的电路布局和布线结构的任何显着变化以及布线层的多层配置的改变。 当从层叠方向的下部观察时，局部布线1和全局布线2,3以顺序的顺序堆叠在半导体基板10上，其中介电层夹在这些层中的相邻层之间。 本地布线1和全局布线2之间的距离被形成为大于全局布线层2和全局布线3之间的距离。因此，提供了一种半导体器件，其特征在于用于驱动的​​驱动电压 全局布线2,3可能低于用于驱动本地布线1内部的驱动电压。

公开(公告)号：US06411548B1

公开(公告)日：2002-06-25

申请号：US09615803

申请日：2000-07-13

申请人： Koji Sakui ,  Mitsuhiro Noguchi

发明人： Koji Sakui ,  Mitsuhiro Noguchi

IPC分类号： G11C1604

CPC分类号： H01L27/11502 ,  G11C11/22 ,  G11C11/223 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/3409 ,  G11C16/3445 ,  H01L27/115

摘要： A memory cell array is comprised of plural cell units. Each cell unit is connected between a bit line and a source line. Each cell unit is comprised of plural series-connected MFSFETs having substantially the same structure. Of the plural MFSFETs, one MFSFET nearest to the bit line and one MFSFET nearest to the source line are used as select gate transistors. The MFSFETs other than the MFSFETs used as the select gate transistors are used as memory cells. Data is stored in each memory cell as the polarization state of the ferroelectric film of the MFSFET.

摘要翻译： 存储单元阵列由多个单元单元构成。 每个单元单元连接在位线和源极线之间。 每个单元单元由具有基本上相同结构的多个串联连接的MFSFET组成。 在多个MFSFET中，最靠近位线的一个MFSFET和最靠近源极线的一个MFSFET被用作选择栅极晶体管。 用作选择栅极晶体管的MFSFET以外的MFSFET用作存储单元。 数据存储在每个存储单元中作为MFSFET的铁电膜的偏振状态。

公开(公告)号：US06278165B1

公开(公告)日：2001-08-21

申请号：US09340149

申请日：1999-06-28

申请人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

发明人： Yukihito Oowaki ,  Mizuki Ono ,  Mitsuhiro Noguchi ,  Daisaburo Takashima ,  Akira Nishiyama

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/78

摘要： In a MIS transistor, the top surfaces of source/drain regions (S/D diffusion layers) formed on a semiconductor substrate 1 are arranged nearer to a gate electrode than a channel plane on the semiconductor substrate, and the top surfaces of the source/drain regions are arranged nearer than the channel plane than the interface between a gate insulator film provided on the upper side of the channel plane and the gate electrode. In this transistor, a groove is selectively formed in the surface of the semiconductor substrate, and a polycrystalline silicon deposited in the groove may be used as a mask to form impurity diffusion layers serving as source/drain regions to laminate and form a gate insulator film of a high dielectric film and a gate electrode. Alternatively, the polycrystalline silicon may be selectively formed to be used as a mask to elevate and form the impurity diffusion layer to laminate and form the gate insulator film and the gate electrode. Thus, it is possible to achieve both of the reduction of the resistance of the S/D diffusion layers and the reduction of the gate parasitic capacitance.

摘要翻译： 在MIS晶体管中，形成在半导体基板1上的源极/漏极区域（S / D扩散层）的上表面布置成比半导体衬底上的沟道平面更靠近栅电极，源极/漏极区域的顶表面 漏区比布置在沟道平面上侧的栅极绝缘膜与栅电极之间的界面更靠近沟道平面。 在该晶体管中，在半导体衬底的表面中选择性地形成沟槽，并且可以将沉积在沟槽中的多晶硅用作掩模，以形成用作源极/漏极区域的杂质扩散层，以层压并形成栅极绝缘膜 的高介电膜和栅电极。 或者，可以选择性地形成多晶硅以用作掩模以升高和形成杂质扩散层以层压并形成栅极绝缘膜和栅电极。 因此，可以实现S / D扩散层的电阻的降低和栅极寄生电容的降低。

公开(公告)号：US6043536A

公开(公告)日：2000-03-28

申请号：US313774

申请日：1999-05-18

申请人： Toshinori Numata ,  Mitsuhiro Noguchi

发明人： Toshinori Numata ,  Mitsuhiro Noguchi

IPC分类号： B82B1/00 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78648

摘要： In a semiconductor device including a full depletion MISFET transistor made by using a SOI layer and intended to stabilize a predetermined threshold value while holding the threshold value sensitivity to fluctuation in thickness of the SOI layer even upon changes in impurity concentration of a channel region of the MISFET transistor by changing a back gate voltage in accordance with the impurity concentration of the channel region, thickness of the SOI layer is determined to reduce changes in threshold value, and impurity concentration of the channel region is measured by using a detector element to adjust the back gate voltage in response to the measured value. Thus, the desired threshold voltage can be maintained.

摘要翻译： 在包括使用SOI层制成并旨在使预定阈值稳定同时将阈值灵敏度保持在SOI层的厚度波动的半导体器件中的情况下，即使即使在SOI层的沟道区域的杂质浓度的变化 通过根据沟道区域的杂质浓度改变背栅极电压来确定MISFET晶体管，确定SOI层的厚度以减小阈值的变化，并且通过使用检测器元件来测量沟道区域的杂质浓度，以调整 响应于测量值的背栅电压。 因此，可以保持期望的阈值电压。