公开(公告)号：US6078983A

公开(公告)日：2000-06-20

申请号：US862322

申请日：1997-05-23

Applicant: Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

Inventor： Makoto Hanawa ,  Tadahiko Nishimukai ,  Osamu Nishii ,  Makoto Suzuki

IPC: G06F15/16 ,  G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F15/167 ,  G06F15/177 ,  G06F13/36

CPC classification number: G06F13/1642 ,  G06F13/1605

Abstract: A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, first and second arbiters, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. When a processor requires data from the memory bank, the processor sends a processor ID with a data access request. When the memory bank sends data in return, the memory bank outputs the processor ID of the request originator with the required data. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access requested need not wait for a previous access request to be finished. According, the throughput of the system can be improved greatly. The first and second arbiters serve to decide ownership of buses.

Abstract translation: 本发明的多处理器系统具有地址总线，数据总线，第一和第二处理器，四个访问队列，第一和第二仲裁器以及被划分成四个存储体的共享存储器。 四个访问队列由用于缓冲通过地址总线发送的多个访问请求地址的先进先出存储器构成。 当处理器需要来自存储体的数据时，处理器发送具有数据访问请求的处理器ID。 当存储体返回数据时，存储体输出请求发起者的处理器ID和所需的数据。 即使连续访问请求被寻址到共享存储器的一个组，请求的后续访问也不需要等待先前的访问请求完成。 据说，系统的吞吐量可以大大提高。 第一和第二仲裁者用于决定公共汽车的所有权。

公开(公告)号：US5301285A

公开(公告)日：1994-04-05

申请号：US940762

申请日：1992-09-04

Applicant: Makoto Hanawa ,  Osamu Nishii ,  Susumu Narita ,  Kunio Uchiyama

Inventor： Makoto Hanawa ,  Osamu Nishii ,  Susumu Narita ,  Kunio Uchiyama

IPC: G06F9/34 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3822

Abstract: A data processor is provided with a first register storing a first half word of one instruction; a second register storing a second half word of the instruction; a first decoder decoding the first half word and at the same time detecting whether there exists an addressing extension portion between the first half word and the second half word; a second decoder decoding the second half word; and, a decode result generating circuit, to which a detection signal of the first decoder indicates whether the addressing extension portion exists. A decode result of the first decoder and a decode result of the second decoder are supplied to the decode result generating circuit. An extension portion register is provided to store the addressing extension portion. When the first decoder detects the addressing extension portion, the decode result generating circuit invalidates the decode result of the second decoder. On the other hand, in the case where there exists no addressing extension portion, the decode result generating circuit judges, on the basis of the detection signal, that the decode result of the second decoder is valid.

Abstract translation: 数据处理器设置有存储一个指令的前半字的第一寄存器; 存储指令的第二个半字的第二寄存器; 解码所述前半字，并且同时检测在所述前半字和所述第二半字之间是否存在寻址扩展部分的第一解码器; 解码所述第二半字的第二解码器; 以及第一解码器的检测信号指示寻址扩展部分是否存在的解码结果生成电路。 第一解码器的解码结果和第二解码器的解码结果被提供给解码结果生成电路。 提供扩展部分寄存器以存储寻址扩展部分。 当第一解码器检测到寻址扩展部分时，解码结果生成电路使第二解码器的解码结果无效。 另一方面，在不存在寻址扩展部的情况下，解码结果生成电路根据检测信号判断第二解码器的解码结果有效。

公开(公告)号：US5283886A

公开(公告)日：1994-02-01

申请号：US950746

申请日：1992-09-24

Applicant: Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Kanji Oishi ,  Jun Kitano ,  Susumu Hatano

Inventor： Osamu Nishii ,  Kunio Uchiyama ,  Hirokazu Aoki ,  Kanji Oishi ,  Jun Kitano ,  Susumu Hatano

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0833

Abstract: Herein disclosed is a multiprocessor system which comprises first and second processors (1001 and 1002), first and second cache memories (100:#1 and #2), an address bus (123), a data bus (126), an invalidating signal line (PURGE:131) and a main memory (1004). The first and second cache memories are operated by the copy-back method. The state of the data of the first cache (100:#1) exists in one state selected from a group consisting of an invalid first state, a valid and non-updated second state and a valid and updated third state. The second cache (100:#2) is constructed like the first cache. When the write access of the first processor hits the first cache, the state of the data of the first cache is shifted from the second state to the third state, and the first cache outputs the address of the write hit and the invalidating signal to the address bus and the invalidating signal line, respectively. When the write access from the first processor misses the first cache, a data of one block is block-transferred from the main memory to the first cache, and the invalidating signal is outputted. After this, the first cache executes the write of the data in the transfer block. In case the first and second caches hold the data in the third state relating to the pertinent address when an address of an access request is fed to the address bus (123), the pertinent cache writes back the pertinent data in the main memory.

Abstract translation: 这里公开了一种多处理器系统，其包括第一和第二处理器（1001和1002），第一和第二高速缓冲存储器（100：＃1和＃2），地址总线（123），数据总线（126），无效信号 线（PURGE：131）和主存储器（1004）。 第一和第二高速缓存存储器通过复制方法操作。 第一高速缓存（100：＃1）的数据的状态存在于从由无效的第一状态，有效和未更新的第二状态以及有效和更新的第三状态组成的组中选择的一个状态中。 第二个缓存（100：＃2）被构造成像第一个缓存。 当第一处理器的写入访问第一高速缓存时，第一高速缓存的数据的状态从第二状态转移到第三状态，并且第一高速缓存将写入命中的地址和无效信号输出到 地址总线和无效信号线。 当来自第一处理器的写访问错过第一高速缓存时，一个块的数据被从主存储器块传输到第一高速缓存，并且输出无效信号。 之后，第一个缓存执行传输块中数据的写入。 在第一和第二高速缓冲存储器将存取请求地址与相关地址相关的第三状态的数据保存到地址总线（123）的情况下，相关高速缓冲存储器将相关数据写回到主存储器中。

公开(公告)号：US07904641B2

公开(公告)日：2011-03-08

申请号：US12123195

申请日：2008-05-19

Applicant: Kunio Uchiyama ,  Osamu Nishii

Inventor： Kunio Uchiyama ,  Osamu Nishii

IPC: G06F12/00

CPC classification number: G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

Abstract: A processor system including: a processor and controller core connected via an internal bus; and a plurality of synchronous memory chips connected to the processor via an external bus; the controller core including a mode register selected by an address signal from the processor core and written with an information by a data signal from the processor core to select the operation mode of the plurality of synchronous memory chips, and a control unit to prescribe the operate mode to the plurality of synchronous memory chips based on the information written in the mode register, wherein the controller core outputs a mode setting signal based on the information written in the mode register or an access address signal from the processor core to the plurality of synchronous memory chips via the external bus selectively; and wherein the clock signal is commonly supplied to the plurality of synchronous memory chips.

Abstract translation: 一种处理器系统，包括：通过内部总线连接的处理器和控制器核; 以及经由外部总线连接到处理器的多个同步存储器芯片; 所述控制器核心包括通过来自所述处理器核心的地址信号选择的模式寄存器，并且通过来自所述处理器核心的数据信号写入信息以选择所述多个同步存储器芯片的操作模式;以及控制单元，用于规定所述操作 模式基于写入模式寄存器中的信息而发送到多个同步存储器芯片，其中控制器核心基于写入模式寄存器中的信息或从处理器核心的存取地址信号向多个同步信号输出模式设置信号 选择性地通过外部总线的存储器芯片; 并且其中所述时钟信号被共同地提供给所述多个同步存储器芯片。

公开(公告)号：US20070061537A1

公开(公告)日：2007-03-15

申请号：US11598661

申请日：2006-11-14

Applicant: Kunio Uchiyama ,  Osamu Nishii

Inventor： Kunio Uchiyama ,  Osamu Nishii

IPC: G06F13/00

CPC classification number: G11C8/18 ,  G11C7/1006 ,  G11C7/1072 ,  G11C8/12 ,  H04N19/423 ,  H04N19/61

Abstract: A chip including: a microprocessor; a control unit coupled to the microprocessor; and interface nodes for coupling a synchronous dynamic memory; wherein the control unit generates command information and the interface nodes output the command information to the synchronous dynamic memory in synchronism with a clock signal, wherein the command information includes a mode register set function which sets mode information to a mode register in the synchronous dynamic memory, and wherein the control unit outputs the mode information to address signal input terminals of the synchronous dynamic memory.

Abstract translation: 芯片包括：微处理器; 耦合到所述微处理器的控制单元; 以及用于耦合同步动态存储器的接口节点; 其中所述控制单元产生命令信息，并且所述接口节点与时钟信号同步地将所述命令信息输出到所述同步动态存储器，其中所述命令信息包括将模式信息设置到所述同步动态存储器中的模式寄存器的模式寄存器设置功能 并且其中所述控制单元将所述模式信息输出到所述同步动态存储器的地址信号输入端子。

公开(公告)号：US07023757B2

公开(公告)日：2006-04-04

申请号：US10373042

申请日：2003-02-26

Applicant: Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

Inventor： Takao Watanabe ,  Kunio Uchiyama ,  Osamu Nishii ,  Naohiko Irie ,  Hiroyuki Mizuno

IPC: G11C8/00 ,  G06F1/26

CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G11C5/147 ,  G11C11/417 ,  Y02D10/171

Abstract: When a leakage current of a circuit block under a non-use state is reduced by means of a power switch, frequent ON/OFF operations of the switch within a short time invite an increase of consumed power, on the contrary. Because a pre-heating time is necessary from turn-on of the switch till the circuit block becomes usable, control of the switch during an operation deteriorates a processing time of a semiconductor device. The switch is ON/OFF-controlled with a task duration time of a CPU core for controlling logic circuits and memory cores as a unit. After the switch is turned off, the switch is again turned on before termination of the task in consideration of the pre-heating time.

公开(公告)号：US07003651B2

公开(公告)日：2006-02-21

申请号：US10017198

申请日：2001-12-18

Applicant: Yuki Kondoh ,  Osamu Nishii

Inventor： Yuki Kondoh ,  Osamu Nishii

IPC: G06F9/32

CPC classification number: G06F9/382 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3802

Abstract: The invention allows the execution of a PC relative branch instruction with displacement is speeded up without changing the instruction operations of existing processors and without requiring new instructions. The branch target address calculation is made faster by calculating the lower portion of the branch target address prior to storing the instruction word in a cache or buffer, and writing the calculation result into the displacement field of the instruction word and into a bit that has been added to the cache or the buffer, such that some calculation is executed simultaneously to be skipped later at the time of execution of the instruction by using the executed calculation result stored in the cache or buffer.

公开(公告)号：US06715090B1

公开(公告)日：2004-03-30

申请号：US09308488

申请日：1999-05-20

Applicant: Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

Inventor： Yonetaro Totsuka ,  Koichiro Ishibashi ,  Hiroyuki Mizuno ,  Osamu Nishii ,  Kunio Uchiyama ,  Takanori Shimura ,  Asako Sekine ,  Yoichi Katsuki ,  Susumu Narita

IPC: G06F130

CPC classification number: G06F1/3296 ,  G06F1/3203 ,  Y02D10/172 ,  Y02D50/20

Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.

Abstract translation: 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。

公开(公告)号：US06424560B1

公开(公告)日：2002-07-23

申请号：US09824232

申请日：2001-04-03

Applicant: Osamu Nishii ,  Motonobu Tonomura ,  Takanobu Tsunoda

Inventor： Osamu Nishii ,  Motonobu Tonomura ,  Takanobu Tsunoda

IPC: G11C1100

Abstract: A small-area associative memory for association by a value resulted from addition, with reduced carry delay, is disclosed. Adjacent 1-bit memory values and a signal depending on adjacent 2 bits of addition-inputs are inputted into a CAM memory cell constructed using MOS transistors, and a hit line is pulled down or pulled up in accordance with the input values.

公开(公告)号：US06292867B1

公开(公告)日：2001-09-18

申请号：US09641913

申请日：2000-08-21

Applicant: Osamu Nishii ,  Nobuyuki Hayashi ,  Noriharu Hiratsuka ,  Tetsuhiko Okada ,  Hiroshi Takeda

Inventor： Osamu Nishii ,  Nobuyuki Hayashi ,  Noriharu Hiratsuka ,  Tetsuhiko Okada ,  Hiroshi Takeda

IPC: G06F1202

CPC classification number: G06F12/0215 ,  G06F13/1631

Abstract: A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.

Abstract translation: 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。