公开(公告)号：US08247848B2

公开(公告)日：2012-08-21

申请号：US12907705

申请日：2010-10-19

申请人： Shoji Kawahito

发明人： Shoji Kawahito

IPC分类号： H01L27/146

CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14656 ,  H04N5/35518 ,  H04N5/3598

摘要： An n-type region as a charge storage region of a photodiode is buried in a substrate. The interface between silicon and a silicon oxide film is covered with a high concentration p-layer and a lower concentration p-layer is formed only in the portion immediately below a floating electrode for signal extraction. Electrons generated by light are stored in the charge storage region, thereby changing the potential of the portion of the p-layer at the surface of the semiconductor region. The change is transmitted through a thin insulating film to the floating electrode by capacitive coupling and read out by a buffer transistor. Initialization of charges is executed by adding a positive high voltage to the gate electrode of a first transfer transistor such that the electrons stored in the charge storage region are transferred to the n+ region and generation of reset noise is protected.

摘要翻译： 作为光电二极管的电荷存储区域的n型区域埋在基板中。 硅和氧化硅膜之间的界面被高浓度p层覆盖，并且较低浓度的p层仅形成在用于信号提取的浮动电极正下方的部分。 由光产生的电子被存储在电荷存储区域中，从而改变在半导体区域的表面处的p层的部分的电位。 该变化通过电容耦合通过薄的绝缘膜透射到浮动电极，并由缓冲晶体管读出。 通过向第一传输晶体管的栅极添加正高电压，使得存储在电荷存储区域中的电子被转移到n +区域并且产生复位噪声被保护来执行电荷的初始化。

公开(公告)号：US08125551B2

公开(公告)日：2012-02-28

申请号：US12477739

申请日：2009-06-03

申请人： Nobuo Nakamura ,  Shoji Kawahito ,  Hiroki Sato ,  Mizuho Higashi

发明人： Nobuo Nakamura ,  Shoji Kawahito ,  Hiroki Sato ,  Mizuho Higashi

IPC分类号： H04N5/335 ,  H04N5/235 ,  H04N3/14

CPC分类号： H04N5/378 ,  H01L27/14609 ,  H04N5/243 ,  H04N5/355 ,  H04N5/374 ,  H04N5/37455 ,  H04N5/37457

摘要： An image sensor controls the gain of a pixel signal on a pixel-by-pixel basis and extends a dynamic range while maintaining a S/N ratio at a favorable level. A column unit in an image sensor is independently detects a level of each pixel signal and independently sets a gain for level of the signal. A photoelectric converting region unit has pixels arranged two-dimensionally with a vertical signal line for each pixel column to output each pixel signal. The column unit is on an output side of the vertical signal line. The column unit for each pixel column has a pixel signal level detecting circuit, a programmable gain control, a sample and hold (S/H) circuit. Gain correction is performed according to a result of a detected level of the pixel signal.

摘要翻译： 图像传感器在逐像素的基础上控制像素信号的增益，并且在保持S / N比在有利水平的同时延伸动态范围。 图像传感器中的列单元独立地检测每个像素信号的电平，并独立地设置信号电平的增益。 光电转换区域单元具有用于每个像素列的垂直信号线二维布置的像素，以输出每个像素信号。 列单元位于垂直信号线的输出侧。 每个像素列的列单元具有像素信号电平检测电路，可编程增益控制，采样和保持（S / H）电路。 根据检测到的像素信号电平的结果进行增益校正。

公开(公告)号：US20110193553A1

公开(公告)日：2011-08-11

申请号：US13064763

申请日：2011-04-13

申请人： Toru Takahashi ,  Shoji Kawahito

发明人： Toru Takahashi ,  Shoji Kawahito

IPC分类号： G01R33/02

CPC分类号： G01D5/145

摘要： A magnetic array sensor circuit to process an output from a magnetic sensor array including a plurality of magnetic sensor elements arranged in an array. The circuit includes a regulating circuit to reduce an offset variation of the output from the magnetic sensor elements arranged in the array.

摘要翻译： 一种用于处理来自包括以阵列布置的多个磁传感器元件的磁传感器阵列的输出的磁阵列传感器电路。 该电路包括调节电路，以减少输出与布置在阵列中的磁传感器元件的偏移偏差。

公开(公告)号：US20110187908A1

公开(公告)日：2011-08-04

申请号：US13056816

申请日：2009-07-31

申请人： Shoji Kawahito ,  Hiroaki Takeshita

发明人： Shoji Kawahito ,  Hiroaki Takeshita

IPC分类号： H04N5/335 ,  H01L27/148 ,  H01J40/14

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14612 ,  H01L27/14641

摘要： The present invention provides a high-speed charge-transfer photodiode encompassing a first conductivity type semiconductor layer (20) serving as a charge-generation region; and a second conductivity type surface-buried region (21a) serving as a charge-transfer region of charges generated by the charge-generation region, wherein a specified direction in the surface-buried region (21a) provided along a plane parallel to a surface of the semiconductor layer (20) is assigned as a charge-transfer direction of the charges, and at least one of a variation of widths of the surface-buried region (21a) measured in an orthogonal direction to the charge-transfer direction and a variation of impurity concentration distributions of the surface-buried region (21a), which are measured along the charge-transfer direction, is determined such that an electric field distribution in the charge-transfer direction is constant.

摘要翻译： 本发明提供一种包含用作电荷产生区域的第一导电类型半导体层（20）的高速电荷转移光电二极管; 以及作为由电荷产生区域产生的电荷的电荷转移区域的第二导电型表面埋藏区域，其中沿着平行于表面的平面设置的表面埋藏区域（21a）中的指定方向 被分配为电荷的电荷传送方向，并且在与电荷传输方向正交的方向上测量的表面埋藏区域（21a）的宽度的变化中的至少一个和 确定沿着电荷转移方向测量的表面埋藏区域（21a）的杂质浓度分布的变化，使得电荷传输方向上的电场分布是恒定的。

公开(公告)号：US07948231B2

公开(公告)日：2011-05-24

申请号：US11792814

申请日：2005-12-06

申请人： Toru Takahashi ,  Shoji Kawahito

发明人： Toru Takahashi ,  Shoji Kawahito

IPC分类号： G01B7/30

CPC分类号： G01D5/145

摘要： A rotation detecting apparatus capable of increasing the angle detecting precision without being affected by an offset signal resulting from a stress in a silicon chip. The rotation detecting apparatus includes a magnetic sensor array and a magnet rotatable in face-to-face relation with the magnetic sensor array. The magnetic sensor array includes a plurality of groups of sensor elements, each group including four sensor elements. The four sensor elements of each combined sensor element group are so arranged as to be oriented vertically and horizontally in four directions and connected parallel to each other.

摘要翻译： 一种旋转检测装置，其能够增加角度检测精度，而不受由硅芯片中的应力引起的偏移信号的影响。 旋转检测装置包括磁传感器阵列和与磁传感器阵列以面对面的关系旋转的磁体。 磁传感器阵列包括多组传感器元件，每组包括四个传感元件。 每个组合的传感器元件组的四个传感器元件被布置成在四个方向上垂直和水平地定向并且彼此平行地连接。

公开(公告)号：US07842978B2

公开(公告)日：2010-11-30

申请号：US11577546

申请日：2005-10-18

申请人： Shoji Kawahito

发明人： Shoji Kawahito

IPC分类号： H01L31/113

CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14656 ,  H04N5/35518 ,  H04N5/3598

摘要： An n-type region as a charge storage region of a photodiode is buried in a substrate. The interface between silicon and a silicon oxide film is covered with a high concentration p-layer and a lower concentration p-layer is formed only in the portion immediately below a floating electrode for signal extraction. Electrons generated by light are stored in the charge storage region, thereby changing the potential of the portion of the p-layer at the surface of the semiconductor region. The change is transmitted through a thin insulating film to the floating electrode by capacitive coupling and read out by a buffer transistor. Initialization of charges is executed by adding a positive high voltage to the gate electrode of a first transfer transistor such that the electrons stored in the charge storage region are transferred to the n+ region and generation of reset noise is protected.

摘要翻译： 作为光电二极管的电荷存储区域的n型区域埋在基板中。 硅和氧化硅膜之间的界面被高浓度p层覆盖，并且较低浓度的p层仅形成在用于信号提取的浮动电极正下方的部分。 由光产生的电子被存储在电荷存储区域中，从而改变在半导体区域的表面处的p层的部分的电位。 该变化通过电容耦合通过薄的绝缘膜透射到浮动电极，并由缓冲晶体管读出。 通过向第一传输晶体管的栅极添加正高电压，使得存储在电荷存储区域中的电子被转移到n +区域并且产生复位噪声被保护来执行电荷的初始化。

公开(公告)号：US07834786B2

公开(公告)日：2010-11-16

申请号：US12436289

申请日：2009-05-06

申请人： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji Kawahito ,  Zheng Liu ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/10

CPC分类号： H03M1/1009 ,  G11C27/026 ,  H03M1/1215

摘要： A sample hold circuit is provided for use in a time-interleaved A/D converter apparatus including a plurality of low-speed pipeline A/D converters which are parallelized. The sample hold circuit includes a sampling capacitor and a sample hold amplifier, and operates to sample and hold an input signal by using a switched capacitor. An adder circuit of the sample hold circuit adds a ramp calibration signal to the input signal, by inputting the ramp calibration signal generated to have a frequency identical to that of a sampling clock signal and a predetermined slope based on the sampling clock signal, into a sample hold amplifier via a calibration capacitor having a capacitance smaller than that of the sampling capacitor.

摘要翻译： 提供了一种采样保持电路，用于并行化的多个低速流水线A / D转换器的时间交错A / D转换装置。 采样保持电路包括采样电容器和采样保持放大器，并且通过使用开关电容器来操作来采样和保持输入信号。 采样保持电路的加法电路通过将产生的具有与采样时钟信号和采样时钟信号的频率相同的频率的斜坡校准信号和基于采样时钟信号的预定斜率输入到输入信号中，将斜坡校准信号添加到 采样保持放大器经由具有小于采样电容器的电容的校准电容器。

公开(公告)号：US07781811B2

公开(公告)日：2010-08-24

申请号：US12065156

申请日：2006-08-30

申请人： Shoji Kawahito ,  Mitsuru Homma

发明人： Shoji Kawahito ,  Mitsuru Homma

IPC分类号： H01L31/062

CPC分类号： H01L27/14603 ,  G01S7/483 ,  G01S17/10 ,  G01S17/89 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

摘要： To transfer signal charges generated by a semiconductor photoelectric conversion element in opposite directions, the center line of a first transfer gate electrode and that of a second transfer gate electrodes are arranged on the same straight line, and a U-shaped first exhausting gate electrode and a second exhausting gate electrode are arranged to oppose to each other. The first exhausting gate electrode exhausts background charges generated by a background light in the charge generation region, and the second exhausting gate electrode exhausts background charges generated by the background light in the charge generation region. The background charges exhausted by the first exhausting gate electrode are received by a first exhausting drain region and the background charges exhausted by the second exhausting gate electrode are received by a first exhausting drain region.

摘要翻译： 为了将由半导体光电转换元件产生的信号电荷沿相反的方向转移，第一传输栅电极的中心线和第二传输栅电极的中心线被布置在相同的直线上，并且U形的第一排气栅电极和 第二排气栅电极被布置成彼此相对。 第一排气栅电极排出由电荷产生区域中的背景光产生的背景电荷，并且第二排气栅电极排出由电荷产生区域中的背景光产生的背景电荷。 由第一排气栅电极耗尽的背景电荷由第一排气漏极区域接收，由第二排气栅电极排出的背景电荷由第一排气区域接收。

公开(公告)号：US20100182176A1

公开(公告)日：2010-07-22

申请号：US12303852

申请日：2007-06-08

申请人： Shoji Kawahito

发明人： Shoji Kawahito

IPC分类号： H03M1/12 ,  H03M1/66

CPC分类号： H03M1/1245 ,  H03M1/00 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/44

摘要： A charge corresponding to an analog signal Vi is accumulated in first and second capacitors 25, 27, respectively. A digital signal VDIGN having a digital value (D1, D0, for example) corresponding to the analog signal Vi is generated. By connecting the second capacitor 27 between an output 21c and an inversion input 21a of an operational amplifier circuit 21 and supplying a first capacitor end 25a with an analog signal VD/A corresponding to the digital signal VDIGN, a first conversion value VOUT1 is generated in the output 21c of the operational amplifier circuit 21. By connecting the first and third capacitors 25, 33 between the output 21c and inversion input 21a of the operational amplifier circuit 21 and supplying a second capacitor end 27a with the analog signal VD/A, a second conversion value VOUT2 is generated in the output 21c of the operational amplifier circuit 21.

摘要翻译： 对应于模拟信号Vi的电荷分别累积在第一和第二电容器25,27中。 产生具有对应于模拟信号Vi的数字值（例如，D1，D0）的数字信号VDIGN。 通过将第二电容器27连接在运算放大器电路21的输出端21c和反相输入端21a之间，并向第一电容器端部25a提供与数字信号VDIGN相对应的模拟信号VD / A，则产生第一转换值VOUT1 运算放大器电路21的输出21c。通过在运算放大器电路21的输出21c和反相输入端21a之间连接第一和第三电容器25,33，并向第二电容器端27a提供模拟信号VD / A， 第二转换值VOUT2在运算放大器电路21的输出21c中产生。

公开(公告)号：US20100073214A1

公开(公告)日：2010-03-25

申请号：US12562664

申请日：2009-09-18

申请人： Shoji KAWAHITO ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

发明人： Shoji KAWAHITO ,  Kazutaka Honda ,  Yasuhide Shimizu ,  Kuniyuki Tani ,  Akira Kurauchi ,  Koji Sushihara ,  Koichiro Mashiko

IPC分类号： H03M1/12 ,  H03F3/45

CPC分类号： H03F3/45237 ,  H03F2203/45094 ,  H03F2203/45356 ,  H03F2203/45481 ,  H03F2203/45551

摘要： A telescopic differential operational amplifier circuit for use in a pipelined A/D converter is provided with two auxiliary differential amplifiers connected to two cascode circuits, each including cascode-connected first to fourth transistors. During the sampling phase, first and second switches are turned on to apply a predetermined bias voltage to the gates of first and fourth transistors, and the input terminal of the differential operational amplifier circuit is set to a common mode voltage. During the hold phase, the first and second switches are turned off so that a voltage of each of the gates of the first and fourth transistors change to follow an input signal inputted via the input terminal with coupling capacitors operating as a level shifter of the input signal. Then the differential operational amplifier circuit performs push-pull operation operative only in a transconductance drive region, and is prevented from operating in a slewing region.

摘要翻译： 在流水线A / D转换器中使用的伸缩差分运算放大器电路设置有两个辅助差分放大器，其连接到两个共源共栅电路，每个包括共源共栅连接的第一至第四晶体管。 在采样阶段期间，第一和第二开关导通以对第一和第四晶体管的栅极施加预定的偏置电压，并且差分运算放大器电路的输入端被设置为共模电压。 在保持阶段期间，第一和第二开关断开，使得第一和第四晶体管的每个栅极的电压改变为跟随经由输入端输入的输入信号，耦合电容器作为输入的电平转换器 信号。 然后，差分运算放大器电路仅在跨导驱动区域中执行推挽操作，并且防止在回转区域中操作。