公开(公告)号：US08307439B2

公开(公告)日：2012-11-06

申请号：US11998838

申请日：2007-11-30

Applicant: Travis T. Schluessler ,  Stephen D. Goglin ,  Erik J. Johnson

Inventor： Travis T. Schluessler ,  Stephen D. Goglin ,  Erik J. Johnson

IPC: G08B23/00 ,  G06F21/00

CPC classification number: G06F21/83 ,  A63F2300/201 ,  A63F2300/206 ,  G06F21/629

Abstract: In general, in one aspect, an add-in card includes inaccessible memory to store an identity key, wherein the identity key is to enable a secure communication link. The add-in card also includes an isolated execution environment and a machine-accessible medium comprising content. The content when executed by the isolated execution environment causes the isolated execution environment to route secure communications between an on-line application and a remote service provider through the isolated execution environment to provide a secure communication link therebetween, detect on-line application code modifications, detect on-line application process flow modifications, and notify, via the secure communication link, the remote service provider when a modification is detected.

Abstract translation: 通常，在一个方面，附加卡包括不可访问的存储器以存储身份密钥，其中身份密钥用于启用安全通信链路。 附加卡还包括隔离的执行环境和包含内容的机器可访问介质。 由隔离的执行环境执行的内容导致隔离执行环境通过隔离执行环境在在线应用和远程服务提供商之间路由安全通信，以在其间提供安全通信链路，检测在线应用代码修改， 检测在线应用程序流程修改，并且在检测到修改时通过安全通信链路通知远程服务提供商。

公开(公告)号：US11010953B2

公开(公告)日：2021-05-18

申请号：US15493195

申请日：2017-04-21

Applicant: Abhishek R. Appu ,  Prasoonkumar Surti ,  Srivallaba Mysore ,  Subhajit Dasgupta ,  Hiroshi Akiba ,  Eric J. Hoekstra ,  Linda L. Hurd ,  Travis T. Schluessler ,  Daren J. Schmidt

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Srivallaba Mysore ,  Subhajit Dasgupta ,  Hiroshi Akiba ,  Eric J. Hoekstra ,  Linda L. Hurd ,  Travis T. Schluessler ,  Daren J. Schmidt

IPC: G06T15/00 ,  G06T15/50 ,  G06T1/20 ,  G06F1/3287 ,  G06F9/54

Abstract: Briefly, in accordance with one or more embodiments, a processor receives an incoming data stream that includes alpha channel data, and a memory stores an application programming interface (API). The API is to route the alpha channel data to a fixed point blending unit to perform one or more blending operations using fixed point representation of the alpha channel data. The API is further to route the incoming data stream to a floating point blending unit to perform operations involving floating point representation of the incoming data.

公开(公告)号：US20180307487A1

公开(公告)日：2018-10-25

申请号：US15493442

申请日：2017-04-21

Applicant: Subramaniam M. Maiyuran ,  Guei-Yuan Lueh ,  Supratim Pal ,  Gang Chen ,  Ananda V. Kommaraju ,  Joy Chandra ,  Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Hong Bin Liao ,  Joydeep Ray ,  Abhishek R. Appu ,  Ankur N. Shah ,  Travis T. Schluessler ,  Jonathan Kennedy ,  Devan Burke

Inventor： Subramaniam M. Maiyuran ,  Guei-Yuan Lueh ,  Supratim Pal ,  Gang Chen ,  Ananda V. Kommaraju ,  Joy Chandra ,  Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Hong Bin Liao ,  Joydeep Ray ,  Abhishek R. Appu ,  Ankur N. Shah ,  Travis T. Schluessler ,  Jonathan Kennedy ,  Devan Burke

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06T1/20

Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

公开(公告)号：US20180285191A1

公开(公告)日：2018-10-04

申请号：US15477050

申请日：2017-04-01

Applicant: Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Eric C. Samson ,  Joydeep Ray ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Ankur N. Shah ,  Altug Koker

Inventor： Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Subramaniam Maiyuran ,  Kiran C. Veernapu ,  Eric C. Samson ,  Joydeep Ray ,  Travis T. Schluessler ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Ankur N. Shah ,  Altug Koker

IPC: G06F11/07

Abstract: Methods and apparatus relating to techniques for reference voltage control based on error detection are described. In an embodiment, modification to a reference voltage (to be supplied to one or more components of a processor) is based at least in part on error detection to be detected for a reference circuit. In another embodiment, modification is made to a power characteristic of a processor in response to a determination that the processor is to execute a safety critical application. The modification may include adjustment to an operating frequency and/or an operating voltage of the processor. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180285158A1

公开(公告)日：2018-10-04

申请号：US15477026

申请日：2017-04-01

Applicant: Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

Inventor： Abhishek R. Appu ,  Altug Koker ,  Balaji Vembu ,  Joydeep Ray ,  Kamal Sinha ,  Prasoonkumar Surti ,  Kiran C. Veernapu ,  Subramaniam Maiyuran ,  Sanjeev S. Jahagirdar ,  Eric J. Asperheim ,  Guei-Yuan Lueh ,  David Puffer ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Josh B. Mastronarde ,  Linda L. Hurd ,  Travis T. Schluessler ,  Tomasz Janczak ,  Abhishek Venkatesh ,  Kai Xiao ,  Slawomir Grajewski

IPC: G06F9/50 ,  G06T1/60 ,  G06T1/20 ,  G06T15/00 ,  G06F9/48 ,  G06F1/32

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US09304570B2

公开(公告)日：2016-04-05

申请号：US13327670

申请日：2011-12-15

Applicant: Travis T. Schluessler ,  Russell J. Fenger

Inventor： Travis T. Schluessler ,  Russell J. Fenger

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/20 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/50 ,  G06F9/5094 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

Abstract translation: 这里描述了一种装置，方法和系统，用于基于测量的工作负载有效地平衡处理元件之间的性能和功率。 如果处理元件的工作负载表明它是瓶颈，则可能会增加其性能。 然而，如果包括处理元件的平台或集成电路已经在功率或热限制下运行，则性能的提高通过另一处理元件的性能的降低或上限来平衡，以保持与功率或热限制的一致性。 因此，即使在多个处理元件在功率或热限制下工作时，通过平衡功率分配来识别和缓解瓶颈。

公开(公告)号：US20150026426A1

公开(公告)日：2015-01-22

申请号：US14510534

申请日：2014-10-09

Applicant: Ravi L. Sahita ,  Travis T. Schluessler

Inventor： Ravi L. Sahita ,  Travis T. Schluessler

IPC: H04L9/32 ,  G06F12/14

CPC classification number: H04L9/3234 ,  G06F9/45558 ,  G06F12/1433 ,  G06F12/1491 ,  G06F21/53 ,  G06F21/72 ,  G06F2009/45587 ,  G06F2221/034 ,  G06F2221/2149 ,  G06F2221/2153

Abstract: A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. The virtualization platform including Virtual Machine Monitor (VMM) managed components coupled to the VMM. One of the VMM managed components is a TPM (Trusted Platform Module). The virtualization platform also includes a plurality of Virtual Machines (VMs). Each of the virtual machines includes a guest Operating System (OS), a TPM device driver (TDD), and at least one security application. The VMM creates an intra-partition in memory for each TDD such that other code and information at a same or higher privilege level in the VM cannot access the memory contents of the TDD. The VMM also maps access only from the TDD to a TPM register space specifically designated for the VM requesting access. Contents of the TPM requested by the TDD are stored in an exclusively VMM-managed protected page table that provides hardware-based memory isolation for the TDD.

公开(公告)号：US20140281615A1

公开(公告)日：2014-09-18

申请号：US13797876

申请日：2013-03-12

Applicant: SELVAKUMAR PANNEER ,  TION A. THOMAS ,  TRAVIS T. SCHLUESSLER ,  ADAM Z. LEIBEL

Inventor： SELVAKUMAR PANNEER ,  TION A. THOMAS ,  TRAVIS T. SCHLUESSLER ,  ADAM Z. LEIBEL

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3215 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/329 ,  G06F9/4881 ,  G06F9/4893 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for monitoring a task of a graphics processing unit (GPU) by a graphics driver, determining if the task is complete, determining an average task completion time for the task if the task is not complete and enabling a sleep state for a processing circuit for a sleep state time if the average task completion time is greater than the sleep state time.

Abstract translation: 各种实施例通常涉及用于通过图形驱动程序监视图形处理单元（GPU）的任务的装置，方法和其他技术，确定任务是否完整，如果任务是任务，则确定任务的平均任务完成时间 如果平均任务完成时间大于睡眠状态时间，则不能完成并为休眠状态时间的处理电路启用睡眠状态。

公开(公告)号：US08099574B2

公开(公告)日：2012-01-17

申请号：US11647025

申请日：2006-12-27

Applicant: Uday Savagaonkar ,  Travis T. Schluessler ,  Hormuzd Khosravi ,  Ravi Sahita ,  Gayathri Nagabhushan ,  David Durham

Inventor： Uday Savagaonkar ,  Travis T. Schluessler ,  Hormuzd Khosravi ,  Ravi Sahita ,  Gayathri Nagabhushan ,  David Durham

IPC: G06F12/00

CPC classification number: G06F12/145

Abstract: Hardware of a virtualized processor based system detecting a specified type of memory access to an identified region of memory and in response to the detecting generating an interrupt for a virtual machine monitor (VMM) of the virtualized processor based system.

Abstract translation: 基于虚拟处理器的系统的硬件检测指定类型的存储器对存储器的识别区域的访问，并且响应于该检测为虚拟处理器系统的虚拟机监视器（VMM）生成中断。

公开(公告)号：US07792960B2

公开(公告)日：2010-09-07

申请号：US11998836

申请日：2007-11-30

Applicant: Stephen D. Goglin ,  Travis T. Schluessler

Inventor： Stephen D. Goglin ,  Travis T. Schluessler

IPC: G06F15/16

CPC classification number: G06F21/552

Abstract: In general, in one aspect, a method is described that includes monitoring data received from input devices. The received data from the input devices associated with an application is copied when the application is active. The data is converted to user commands. Commands used to update the application are received from the application. The converted user commands are compared to the commands from the application. Mismatching commands are reported to a remote server.

Abstract translation: 通常，在一个方面，描述了一种包括监视从输入设备接收的数据的方法。 当应用程序处于活动状态时，复制与应用程序相关联的输入设备的数据。 数据转换为用户命令。 从应用程序接收用于更新应用程序的命令。 转换的用户命令与应用程序的命令进行比较。 不匹配命令报告给远程服务器。