中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

2347 records (took 0.042 seconds)

    Dynamic port handling for isolated modules and dynamic function exchange
    43.
    发明授权
    Dynamic port handling for isolated modules and dynamic function exchange 有权

    公开(公告)号：US12026444B2

    公开(公告)日：2024-07-02

    申请号：US17522834

    申请日：2021-11-09

    Applicant: Xilinx, Inc.

    Inventor： Hao Yu ,  Jun Liu

    IPC: G06F30/343 ,  G06F30/327 ,  G06F30/347

    CPC classification number: G06F30/343 ,  G06F30/327 ,  G06F30/347

    Abstract: Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).

    Systems and methods to transport memory mapped traffic amongst integrated circuit devices
    44.
    发明授权
    Systems and methods to transport memory mapped traffic amongst integrated circuit devices 有权

    公开(公告)号：US12019576B2

    公开(公告)日：2024-06-25

    申请号：US17879675

    申请日：2022-08-02

    Applicant: XILINX, INC.

    Inventor： Krishnan Srinivasan ,  Ygal Arbel ,  Sagheer Ahmad ,  Abbas Morshed

    IPC: G06F13/40

    CPC classification number: G06F13/4027 ,  G06F2213/40

    Abstract: Embodiments herein describe a decentralized chip-to-chip (C2C) interface architecture to transport memory mapped traffic amongst heterogeneous IC devices in a packetized, scalable, and configurable manner. An IC chip may include functional circuitry that exchanges memory-mapped traffic with an off-chip device, a NoC that packetizes and de-packetizes memory-mapped traffic and routes the packetized memory-mapped traffic between the functional circuitry and the off-chip device, and NoC inter-chip bridge (NICB) circuitry that interfaces between the NoC and the off-chip device over C2C interconnections. The NICB circuitry may be configurable in a full mode to map packetized memory-mapped traffic to the C2C interconnections in a 1:1 fashion and in a compressed to map packetized memory-mapped traffic to the C2C interconnections in a less-than 1:1 fashion.

    Lock-stepping asynchronous logic
    45.
    发明授权
    Lock-stepping asynchronous logic 有权

    公开(公告)号：US12019526B2

    公开(公告)日：2024-06-25

    申请号：US17746843

    申请日：2022-05-17

    Applicant: XILINX, INC.

    Inventor： David Tran ,  Aditi R. Ganesan ,  Anurag Goyal

    IPC: H03L7/081 ,  G06F11/16

    CPC classification number: G06F11/1679 ,  H03L7/0814

    Abstract: Methods and systems to detect a metastable condition and suppress/mask a signal during the metastable condition. The metastable condition may arise from asynchronous sampling. Techniques disclosed herein may be configured to enable asynchronous lock-stepping, where outputs of redundant circuit blocks of a first clock domain are received at input nodes of a second clock domain. In the second clock domain, logic states at the input nodes are compared to detect errors, and results of the comparison are masked during transitions at the input nodes. Masking may be constrained to situations where logic states at the input nodes differ.

    PROGRAMMABLE DATA MOVEMENT PROCESSOR FOR COLLECTIVE COMMUNICATION OFFLOAD
    47.
    发明公开
    PROGRAMMABLE DATA MOVEMENT PROCESSOR FOR COLLECTIVE COMMUNICATION OFFLOAD 审中-公开

    公开(公告)号：US20240176652A1

    公开(公告)日：2024-05-30

    申请号：US18060438

    申请日：2022-11-30

    Applicant: Xilinx, Inc.

    Inventor： Lucian Petrica ,  Kenneth O'Brien

    IPC: G06F9/48 ,  G06F9/445 ,  G06F9/54

    CPC classification number: G06F9/4881 ,  G06F9/44505 ,  G06F9/544

    Abstract: A system includes a network-on-chip (NoC). The system includes a protocol offload engine coupled to the NoC. The protocol offload engine is configured to generate packets of data for a selected protocol. The system includes a data movement processor coupled to the network-on-chip. The data movement processor is configured to receive a microcode instruction and, in response to the microcode instruction, establish data paths in the NoC that communicatively link a plurality of circuits involved in data transfers of a collective communication operation specified by the microcode instruction. The plurality of circuits include the protocol offload engine. The system includes a network transceiver coupled to the protocol offload engine. The network transceiver is configured to send the packets of data formatted by the protocol offload engine.

    INTEGRATED CIRCUIT PROTECTION USING STACKED DIES
    48.
    发明公开
    INTEGRATED CIRCUIT PROTECTION USING STACKED DIES 审中-公开

    公开(公告)号：US20240163092A1

    公开(公告)日：2024-05-16

    申请号：US17985736

    申请日：2022-11-11

    Applicant: XILINX, INC.

    Inventor： James D. WESSELKAMPER ,  Thomas Paul LEBOEUF ,  Steve E. MCNEIL ,  Jason J. MOORE ,  James ANDERSON

    IPC: H04L9/08 ,  H01L23/00 ,  H01L25/18

    CPC classification number: H04L9/088 ,  H01L23/576 ,  H01L25/18 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2224/16225

    Abstract: Stacked integrated circuit devices, chip packages and methods for operating a chip package are described herein that provide an increased level of backside protection from physical attacks that could compromise confidentiality or authentication of the integrated circuit device. In one example, a chip stack includes a sacrificial integrated circuit (IC) die stacked with a primary IC die. The sacrificial IC die includes a first split key information source. The primary IC die has security circuitry configured to generate an encryption key based at least in part on first split key information transmitted from the sacrificial IC die across a die-to-die interface to the primary IC die. Separation of the dies to probe or modify of the primary IC die would cause the destruction of split key information required to operate the functional circuitry of the primary IC die.

    METHOD FOR FAULT DETECTION IN SAFETY MECHANISMS
    49.
    发明公开
    METHOD FOR FAULT DETECTION IN SAFETY MECHANISMS 审中-公开

    公开(公告)号：US20240160818A1

    公开(公告)日：2024-05-16

    申请号：US17985735

    申请日：2022-11-11

    Applicant: XILINX, INC.

    Inventor： Federico VENINI ,  David TRAN

    IPC: G06F30/33 ,  G06F30/323

    CPC classification number: G06F30/33 ,  G06F30/323 ,  G06F2119/02

    Abstract: Safety mechanisms are embedded into a System on a Chip (SoC) and are operable to detect faults present in the logic circuitry in the SoC. Various types of faults in logic circuitry can occur, for example, a bit stuck at 0 or 1, or a transient or temporary fault due to radiation impacting the SoC. SoC devices are required to meet certain automotive safety integrity standards. The most stringent automotive safety integrity level requires that 90% of random latent faults are detected in all relevant logic, including all safety mechanism. Examples disclosed include hardware based checkers and hardware or software based pattern generation methods that achieve high online fault coverage in safety mechanism circuitry used for functional safety. A hardware based safety mechanism monitors the logic circuitry during operation. Any time the safety mechanism detects any faults in the logic circuitry, a fault notification is propagated to upstream logic.

Patent Agency Ranking