公开(公告)号：US20080137395A1

公开(公告)日：2008-06-12

申请号：US11764432

申请日：2007-06-18

Applicant: In-jun Hwang ,  Young-jin Cho ,  Sung-hoon Choa ,  Kee-won Kim ,  Kwang-seok Kim

Inventor： In-jun Hwang ,  Young-jin Cho ,  Sung-hoon Choa ,  Kee-won Kim ,  Kwang-seok Kim

IPC: G11C19/00

CPC classification number: G11C11/15 ,  G11C19/0808 ,  G11C19/0841

Abstract: Provided are a data storage device using magnetic domain wall movement and a method of operating the data storage device. The data storage device includes a first magnetic layer for writing data having two magnetic domains magnetized in opposite directions to each other and a second magnetic layer for storing data formed on at least one side of the first magnetic layer. The data storage device may further include a data recording device connected to both ends of the first magnetic layer and the end of the second magnetic layer which is not adjacent to the first magnetic layer, a read head formed a predetermined distance from the end of the second magnetic layer which is not adjacent to the first magnetic layer, and a current detector connected to the read head and the data recording device.

Abstract translation: 提供了使用磁畴壁移动的数据存储装置和操作数据存储装置的方法。 数据存储装置包括用于写入具有彼此相反方向磁化的两个磁畴的数据的第一磁性层和用于存储形成在第一磁性层的至少一侧上的数据的第二磁性层。 数据存储装置还可以包括连接到第一磁性层的两端和不与第一磁性层相邻的第二磁性层的端部的数据记录装置，从头部的端部形成预定距离的读取头 与第一磁性层不相邻的第二磁性层和连接到读取头和数据记录装置的电流检测器。

公开(公告)号：US20070198618A1

公开(公告)日：2007-08-23

申请号：US11708352

申请日：2007-02-21

Applicant: Kee-won Kim ,  Tae-wan Kim ,  Young-jin Cho ,  In-jun Hwang

Inventor： Kee-won Kim ,  Tae-wan Kim ,  Young-jin Cho ,  In-jun Hwang

IPC: G06F15/02

CPC classification number: G11C11/16 ,  G11C19/0808

Abstract: Example embodiments may provide a magnetic memory device. The example embodiment magnetic memory devices may include a plurality of memory tracks, bit lines, connectors, a first input portion, and/or selectors. The memory track(s) may be stacked on a substrate to form a multi-stack. A plurality of magnetic domains may be formed in the memory track so that a data bit may be represented by a magnetic domain and may be stored in an array. The bit line(s) may be formed along respective memory tracks. The connector(s) may form a magnetic tunnel junction (MTJ) cell with one data bit region of the memory track. The first input portion may be electrically connected to each memory track and may input a magnetic domain motion signal to move data stored on a data bit region of the memory track to an adjoining data bit region. The selector(s) may select a memory track from a plurality of memory tracks on which a reading and/or writing operation may to be performed.

Abstract translation: 示例性实施例可以提供磁存储器装置。 示例性实施例磁存储器件可以包括多个存储器轨道，位线，连接器，第一输入部分和/或选择器。 存储器轨道可以堆叠在衬底上以形成多堆叠。 可以在存储器轨道中形成多个磁畴，使得数据位可以由磁畴表示并且可以存储在阵列中。 位线可以沿着各个存储器轨道形成。 连接器可以形成具有存储器轨道的一个数据位区域的磁性隧道结（MTJ）单元。 第一输入部分可以电连接到每个存储器轨道，并且可以输入磁畴运动信号以将存储在存储器轨道的数据位区域上的数据移动到相邻的数据位区域。 选择器可以从其上可以执行读取和/或写入操作的多个存储器轨道中选择存储器轨道。

公开(公告)号：US20060289921A1

公开(公告)日：2006-12-28

申请号：US11514248

申请日：2006-09-01

Applicant: Jung-hyun Lee ,  Yo-sep Min ,  Young-jin Cho

Inventor： Jung-hyun Lee ,  Yo-sep Min ,  Young-jin Cho

IPC: H01L29/94

CPC classification number: H01L28/56 ,  H01L21/02186 ,  H01L21/02197 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/3141 ,  H01L21/321 ,  H01L27/0629 ,  H01L28/55 ,  H01L28/65

Abstract: A capacitor for use in a semiconductor device, a method of fabricating the capacitor, and an electronic device adopting the capacitor, wherein the capacitor includes upper and lower electrodes, each formed of a platinum group metal; a thin dielectric layer disposed between the upper and lower electrodes; and a buffer layer disposed between the lower electrode and the thin dielectric layer, the buffer layer including a metal oxide of Group 3, 4, or 13. In the capacitor of the present invention, oxidization of the lower electrode may be suppressed, and excellent characteristics of the thin dielectric layer may be maintained.

Abstract translation: 一种用于半导体器件的电容器，制造该电容器的方法以及采用该电容器的电子器件，其中该电容器包括由铂族金属形成的上下电极; 设置在上电极和下电极之间的薄介电层; 以及设置在下电极和薄电介质层之间的缓冲层，缓冲层包括第3,4或13族的金属氧化物。在本发明的电容器中，可以抑制下电极的氧化，优异的 可以保持薄介电层的特性。

公开(公告)号：US20050191514A1

公开(公告)日：2005-09-01

申请号：US10953267

申请日：2004-09-30

Applicant: Yo-sep Min ,  Young-jin Cho

Inventor： Yo-sep Min ,  Young-jin Cho

IPC: C23C16/40 ,  B32B9/00 ,  C23C16/455 ,  H01B3/12 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/02156 ,  C23C16/401 ,  H01L21/02153 ,  H01L21/0228 ,  H01L21/31691 ,  Y10T428/12597 ,  Y10T428/12611

Abstract: An amorphous dielectric film for use in a semiconductor device, such as a DRAM, and a method of manufacturing the amorphous dielectric film, includes bismuth (Bi), titanium (Ti), silicon (Si), and oxide (O). The amorphous dielectric film may have a dielectric constant of approximately 60 or higher. The amorphous dielectric film may be expressed by the chemical formula Bi1-x-yTiySiyOz, where 0.2

Abstract translation: 用于诸如DRAM的半导体器件中的非晶体介电膜以及制造非晶体介质膜的方法包括铋（Bi），钛（Ti），硅（Si）和氧化物（O）。 非晶介质膜可以具有大约60或更高的介电常数。 非晶介质膜可以由化学式Bi 1-xy Ti y Si y O z Z z表示， 其中0.2

公开(公告)号：US09933424B2

公开(公告)日：2018-04-03

申请号：US14237518

申请日：2012-08-07

Applicant: Young Bae Park ,  Hyo Soo Kim ,  Yoo Wook Kwon ,  Sahmin Lee ,  Hyun Chae Lee ,  Young Jin Cho ,  Sang Eun Lee ,  Jun Ho Chung

Inventor： Young Bae Park ,  Hyo Soo Kim ,  Yoo Wook Kwon ,  Sahmin Lee ,  Hyun Chae Lee ,  Young Jin Cho ,  Sang Eun Lee ,  Jun Ho Chung

IPC: G01N33/53 ,  G01N33/564 ,  G01N33/68

CPC classification number: G01N33/564 ,  G01N33/6863 ,  G01N2333/715

Abstract: The present invention concerns a human resistin receptor. More particularly, the present invention provides a method for screening a receptor of human resistin protein, a method for preventing or treating an inflammatory disease and arteriosclerosis using an expression- or activity-regulator for a human resistin receptor, and a pharmaceutical composition including an expression- or activity-regulator for the human resistin receptor. The method for screening a human resistin protein receptor according to the present invention enables separation of a receptor which directly binds to resistin from human monocyte, reveals a mechanism of signal transduction of the resistin receptor, and therefore, is expected to contribute to regulation of an inflammatory effect of monocyte, molecular detection of causes for vascular inflammation and arteriosclerosis, and developments of prevention and a treating agent for an inflammatory disease and arteriosclerosis.

公开(公告)号：US20160299525A1

公开(公告)日：2016-10-13

申请号：US14995834

申请日：2016-01-14

Applicant: YOUNG-JIN CHO ,  JAE-GEUN PARK ,  YOUNG-KWANG YOO ,  SOON-SUK HWANG

Inventor： YOUNG-JIN CHO ,  JAE-GEUN PARK ,  YOUNG-KWANG YOO ,  SOON-SUK HWANG

IPC: G06F1/10

CPC classification number: G06F1/10 ,  G06F1/04 ,  G06F5/06

Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

Abstract translation: 一种存储器系统，包括具有通道通道的存储器组的存储器控​​制器。 每个通道接口将控制，地址和/或数据（CAD）信号与从输入时钟导出的从时钟同步地传送到与频道连接的存储器组。 通过应用信道接口专用相位/频率调制或时间延迟来唯一地产生各种从时钟，使得各个CAD信号的特征在于倾斜的转换时序。

公开(公告)号：US09371765B2

公开(公告)日：2016-06-21

申请号：US14232807

申请日：2013-03-22

Applicant: Hee-Sung Yang ,  Joon-Ho Ko ,  Chan-Do Park ,  Seok-Lyong Song ,  Jae-Woo Lee ,  Sung-Young Lee ,  Jai-Hyun Park ,  Kyoung-Jae Kim ,  Seung-Han Han ,  Young-Jin Cho ,  Tae-Min Kim ,  Ju-Yong Jung

Inventor： Hee-Sung Yang ,  Joon-Ho Ko ,  Chan-Do Park ,  Seok-Lyong Song ,  Jae-Woo Lee ,  Sung-Young Lee ,  Jai-Hyun Park ,  Kyoung-Jae Kim ,  Seung-Han Han ,  Young-Jin Cho ,  Tae-Min Kim ,  Ju-Yong Jung

IPC: B01D50/00 ,  F01N3/28 ,  F01N3/022 ,  F01N3/035 ,  B01D53/94

CPC classification number: F01N3/281 ,  B01D53/9413 ,  B01D2255/20707 ,  B01D2255/20723 ,  B01D2255/20776 ,  B01D2255/2092 ,  F01N3/022 ,  F01N3/035 ,  F01N2330/02 ,  F01N2330/22 ,  F01N2510/06

Abstract: The present invention relates to a metal filter for purifying the exhaust gas from a ship, and a preparation method thereof. The purpose of the present invention is to provide: a metal filter for purifying the exhaust gas from a ship, capable of reducing nitrogen oxide by 85% or more at 250-300° C.; and a preparation method thereof. The metal filter for removing nitrogen oxide contained in the exhaust gas from a ship of the present invention comprises an integrated catalyst, wherein a metal substrate comprising irregularities is coated with a low temperature active catalyst in which vanadium (V), tungsten (W) and alumina sol are supported in a Ti-pillared clay (Ti-PILC) powdered support.

Abstract translation: 本发明涉及一种用于净化船舶废气的金属过滤器及其制备方法。 本发明的目的是提供一种用于净化来自船舶的废气的金属过滤器，其能够在250-300℃下将氮氧化物还原85％以上。 及其制备方法。 用于除去本发明船舶废气中所含的氮氧化物的金属过滤器包括一体化催化剂，其中包含不规则的金属基体涂覆有低温活性催化剂，其中钒（V），钨（W）和 氧化铝溶胶负载在钛柱状粘土（Ti-PILC）粉末状载体中。

公开(公告)号：US20150347331A1

公开(公告)日：2015-12-03

申请号：US14689400

申请日：2015-04-17

Applicant: Jae-Geun Park ,  Young-Jin Cho

Inventor： Jae-Geun Park ,  Young-Jin Cho

IPC: G06F13/28 ,  G06F13/16

Abstract: A method of interfacing a memory controller and a memory device in a memory system includes transmitting a control signal between the memory controller and the memory device using a time division multiplexing (TDM) communication process, and transmitting data between the memory controller and the memory device using a serializer/deserializer (SERDES) communication process. Data communication in the memory system is performed via a physical channel and a plurality of virtual channels corresponding to the physical channel.

Abstract translation: 将存储器控制器与存储器系统中的存储器件接口的方法包括使用时分复用（TDM）通信处理在存储器控制器和存储器件之间传输控制信号，以及在存储器控制器和存储器件之间传输数据 使用串行器/解串器（SERDES）通信过程。 存储器系统中的数据通信通过物理信道和对应于物理信道的多个虚拟信道来执行。

公开(公告)号：US20150303114A1

公开(公告)日：2015-10-22

申请号：US14790391

申请日：2015-07-02

Applicant: Sang-moon LEE ,  Young-jin CHO

Inventor： Sang-moon LEE ,  Young-jin CHO

IPC: H01L21/8258 ,  H01L29/20 ,  H01L21/8238 ,  H01L21/306 ,  H01L27/06 ,  H01L21/02 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L21/8258 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/30625 ,  H01L21/8238 ,  H01L27/0605 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/15 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267

Abstract: A complementary metal oxide semiconductor (CMOS) device includes an n-type first transistor on a silicon substrate, the n-type first transistor including a Group III-V compound semiconductor substrate, and a p-type second transistor on the silicon substrate, the p-type second transistor including a germanium based substrate.

Abstract translation: 互补金属氧化物半导体（CMOS）器件包括在硅衬底上的n型第一晶体管，n型第一晶体管包括III-V族化合物半导体衬底和在硅衬底上的p型第二晶体管， p型第二晶体管，包括基于锗的衬底。

公开(公告)号：US20150255592A1

公开(公告)日：2015-09-10

申请号：US14718968

申请日：2015-05-21

Applicant: Young-jin CHO ,  Kyoung-yeon KIM ,  Sang-moon LEE ,  Ki-ha HONG ,  Eui-chul HWANG

Inventor： Young-jin CHO ,  Kyoung-yeon KIM ,  Sang-moon LEE ,  Ki-ha HONG ,  Eui-chul HWANG

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/66 ,  H01L29/12 ,  H01L29/20

CPC classification number: H01L29/7784 ,  H01L21/02538 ,  H01L29/122 ,  H01L29/127 ,  H01L29/158 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42376 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/785

Abstract: A semiconductor device including a group III-V barrier and a method of manufacturing the semiconductor device, the semiconductor device including: a substrate, insulation layers formed to be spaced apart on the substrate, a group III-V material layer for filling the space between the insulation layers and having a portion protruding higher than the insulation layers, a barrier layer for covering the side and upper surfaces of the protruding portion of the group III-V material layer and having a bandgap larger than that of the group III-V material layer, a gate insulation film for covering the surface of the barrier layer, a gate electrode formed on the gate insulation film, and source and drain electrodes formed apart from the gate electrode. The overall composition of the group III-V material layer is uniform. The barrier layer may include a group III-V material for forming a quantum well.