摘要:
A first embodiment of the invention relates to a method for evaluating the quality of structures on an integrated circuit wafer. Test structures formed on either on the integrated or on a test wafer are exposed to an electron beam and an electron-beam activated chemical etch. The electron-beam activated etching gas or vapor etches the test structures, which are analyzed after etching to determine a measure of quality of the test structures. The measure of quality may be used in a statistical process control to adjust the parameters used to form device structures on the integrated circuit wafer. The test structures are formed on an integrated circuit wafer having two or more die. Each die has one or more integrated circuit structures. The test structures are formed on scribe lines between two or more adjacent die. Each test structure may correspond in dimensions and/or composition to one or more of the integrated circuit structures.
摘要:
Embodiments of the invention contemplate the formation of a low cost solar cell using a novel electroplating apparatus and method to form a metal contact structure having metal lines formed using an electrochemical plating process. The apparatus and methods described herein remove the need to perform the often costly processing steps of performing a mask preparation and formation steps, such as screen printing, lithographic steps and inkjet printing steps, to form a contact structure. The resistance of interconnects formed in a solar cell device greatly affects the efficiency of the solar cell. It is thus desirable to form a solar cell device that has a low resistance connection that is reliable and cost effective. Therefore, one or more embodiments of the invention described herein are adapted to form a low cost and reliable interconnecting layer using an electrochemical plating process containing a common metal, such as copper. Embodiments of the invention may provide an apparatus and method of forming a solar cell device that utilizes a reusable masking device during one or more electrochemical deposition steps.
摘要:
Structural modification using electron beam activated chemical etch (EBACE) is disclosed. A target or portion thereof may be exposed to a gas composition of a type that etches the target when the gas composition and/or target are exposed to an electron beam. By directing an electron beam toward the target in the vicinity of the gas composition, an interaction between the electron beam and the gas composition etches a portion of the target exposed to both the gas composition and the electron beam. Structural modifications of the target may be conducted by means of etching due to interaction between the electron beam and gas composition.
摘要:
The present invention relates to the semiconductor device fabrication industry. More particularly a semiconductor device, having an interim reduced-oxygen Cu—Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35). The reduction of electromigration in copper interconnect lines (35) is achieved by decreasing the drift velocity in the copper line (35)/via (6), thereby decreasing the copper migration rate as well as the void formation rate, by using an interim conformal Cu-rich Cu—Zn alloy thin film (30) electroplated on a Cu surface (20) from a stable chemical solution, and by controlling the Zn-doping thereof, which improves also interconnect reliability and corrosion resistance.
摘要:
In one embodiment, a method for depositing a capping layer on a substrate surface containing a copper layer is provided which includes exposing the substrate surface to a zinc solution to form a zinc layer on the copper layer. The method further includes exposing the substrate surface to a silver solution to form a silver layer on the zinc layer, and depositing the capping layer on the silver layer by an electroless deposition process. A second silver layer may be formed on the capping layer, if desired. In another embodiment, a composition of a deposition solution to deposit a cobalt tungsten alloy is disclosed. The deposition solution includes CaWO4, a cobalt source in a range from about 50 mM to about 500 mM, a complexing agent in a range from about 100 mM to about 700 mM and a buffering agent in a range from about 50 mM to about 500 mM.
摘要翻译:在一个实施例中,提供了一种用于在包含铜层的衬底表面上沉积覆盖层的方法,其包括将衬底表面暴露于锌溶液以在铜层上形成锌层。 该方法还包括将衬底表面暴露于银溶液以在锌层上形成银层,并通过无电沉积工艺将覆盖层沉积在银层上。 如果需要,可以在覆盖层上形成第二银层。 在另一个实施方案中,公开了沉积钴钨合金的沉积溶液的组合物。 沉积溶液包括CaWO 4 SO 4,钴源在约50mM至约500mM的范围内,络合剂在约100mM至约700mM的范围内,缓冲剂的范围 约50mM至约500mM。
摘要:
The reliability and electromigration resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer with at least one alloying element for the metal of the feature, and then uniformly diffusing at least a minimum amount of the at least one alloying element of the at least one thin layer for a predetermined minimum depth below the upper surface of the features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer. The invention finds particular utility in “back-end” metallization processing of high-density integrated circuit semiconductor devices having sub-micron dimensioned metallization features.
摘要:
A method of fabricating a semiconductor device, having an interim reduced-oxygen Cu-Zn alloy thin film (30) electroplated on a blanket Cu surface (20) disposed in a via (6) by electroplating, using an electroplating apparatus, the Cu surface (20) in a unique chemical solution containing salts of Zn and Cu, their complexing agents, a pH adjuster, and surfactants; and annealing the interim electroplated Cu—Zn alloy thin film (30); filling the via (6) with further Cu (26); annealing and planarizing the interconnect structure (35); and a semiconductor device thereby formed. The reduction of electromigration in copper interconnect lines (35) is achieved by decreasing the drift velocity in the copper line (35)/via (6), thereby decreasing the copper migration rate as well as the void formation rate, by using an interim conformal Cu-rich Cu—Zn alloy thin film (30) electroplated on a Cu surface (20) from a stable chemical solution, and by controlling the Zn-doping thereof, which improves also interconnect reliability and corrosion resistance.
摘要:
For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material. In that case, a ratio of the tin ion concentration to the palladium ion concentration in the activation bath is adjusted to decrease with an amount of silicon atoms of the layer of silicon rich material deposited on the layer of diffusion barrier material. The present invention may be practiced to particular advantage when the layer of seed material and the conductive fill material are comprised of copper.
摘要:
A method for manufacturing a field effect transistor (100) includes forming a gate structure (104) on a surface of a semiconductor substrate and forming first and second spacers (126, 126) on opposing sides of the gate structure. The method further includes etching a top portion of the gate structure and the first and second spacers to define a trench (1502). Subsequently, by a damascene process, at least a portion of the trench is filed with a barrier-high conductivity metal such as copper (1604) to form a T-gate.
摘要:
For filling an interconnect opening of an integrated circuit formed on a semiconductor substrate, an underlying material is formed at any exposed walls of the interconnect opening. A sacrificial layer of protective material is formed on the underlying material at the walls of the interconnect opening. The underlying material and the sacrificial layer of protective material are formed without a vacuum break. The protective material of the sacrificial layer is soluble in an acidic catalytic solution used for depositing a catalytic seed layer. The semiconductor substrate having the interconnect opening is placed within an acidic catalytic solution for depositing a catalytic seed layer. The sacrificial layer of protective material is dissolved away from the underlying material by the acidic catalytic solution such that the underlying material is exposed to the acidic catalytic solution. A catalytic seed layer formed from the acidic catalytic solution is deposited on the exposed underlying material at the walls of the interconnect opening. The conductive fill for filling the interconnect opening is grown from the catalytic seed layer by electroless deposition. The present invention may be used to particular advantage when the underlying material is comprised of tantalum as a diffusion barrier material, and when the protective material of the sacrificial layer is comprised of magnesium. In that case, the acidic catalytic solution includes palladium chloride and/or tin chloride with hydrochloric acid for dissolving the sacrificial layer of protective material.