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    High temperature stable ohmic contact to gallium arsenide
    43.
    发明授权
    High temperature stable ohmic contact to gallium arsenide 失效
    高温稳定的欧姆接触砷化镓

    公开(公告)号：US4593307A

    公开(公告)日：1986-06-03

    申请号：US509732

    申请日：1983-06-30

    Applicant: Hans S. Rupprecht ,  Sandip Tiwari

    Inventor： Hans S. Rupprecht ,  Sandip Tiwari

    IPC: H01L29/43 ,  H01L21/28 ,  H01L21/285 ,  H01L29/45 ,  H01L23/48

    CPC classification number: H01L21/28575 ,  H01L29/452 ,  Y10S148/084 ,  Y10S148/14

    Abstract: This invention relates generally to ohmic contacts to substrates made of III-V compounds and to a process for fabricating such contacts. More specifically, the invention is directed to a contact to gallium arsenide having a given level of n-type dopant therein, a region of the substrate doped with germanium and a layer of a germanide of a refractory metal selected from the group consisting of molybdenum, tungsten and tantalum disposed on the substrate. Still more specifically, the invention relates to an ohmic contact to gallium arsenide which includes an interface region of germanium heavily doped with arsenic disposed between the region doped with germanium and the layer of germanide. The contact is formed by evaporating germanium and a refractory metal selected from the group consisting of molybdenum, tungsten and tantalum on the surface of an n-type gallium arsenide substrate and sintering the substrate in a reducing atmosphere for a time and at a temperature sufficient to form the first-to-form germanide of the refractory metal. The resulting contact is stable, has a very low contact resistance and may be subjected to later high temperature processing steps without affecting its characteristics.

    Abstract translation: 本发明一般涉及由III-V化合物制成的衬底的欧姆接触以及制造这种接触的方法。 更具体地，本发明涉及其中具有给定水平的n型掺杂剂的砷化镓的接触，掺杂有锗的衬底的区域和选自钼， 设置在基板上的钨和钽。 更具体地，本发明涉及对砷化镓的欧姆接触，其包括重掺杂砷的锗的界面区域，其设置在掺杂有锗的区域和锗化物层之间。 接触是通过在n型砷化镓衬底的表面上蒸发锗和选自钼，钨和钽的难熔金属形成的，并在还原气氛中烧结衬底一段时间并在足以 形成难熔金属的第一个到形式的锗化物。 所得到的接触是稳定的，具有非常低的接触电阻并且可以经受稍后的高温处理步骤而不影响其特性。

    Electro-mechanical transistor
    45.
    发明授权
    Electro-mechanical transistor 有权
    机电晶体管

    公开(公告)号：US08080839B2

    公开(公告)日：2011-12-20

    申请号：US12549906

    申请日：2009-08-28

    Applicant: Sandip Tiwari ,  Moon-Kyung Kim ,  Joshua Mark Rubin ,  Soo-Doo Chae ,  Choong-Man Lee ,  Ravishankar Sundararaman

    Inventor： Sandip Tiwari ,  Moon-Kyung Kim ,  Joshua Mark Rubin ,  Soo-Doo Chae ,  Choong-Man Lee ,  Ravishankar Sundararaman

    IPC: H01L29/84

    CPC classification number: H01L49/00 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00

    Abstract: An electro-mechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.

    Abstract translation: 机电晶体管包括彼此间隔开的源电极和漏电极。 源极柱位于衬底和源电极之间。 漏极柱位于衬底和漏电极之间。 可移动通道与源电极和漏电极间隔开。 门纳米柱位于可移动通道和基板之间。 第一电介质层位于可移动沟道和栅极纳米柱之间。 第二电介质层位于源极柱和源极之间。 第三介电层位于漏极柱和漏极之间。

    Shape memory device
    46.
    发明申请
    Shape memory device 有权
    形状记忆装置

    公开(公告)号：US20070086237A1

    公开(公告)日：2007-04-19

    申请号：US11528712

    申请日：2006-09-27

    Applicant: Sandip Tiwari ,  Chung Kim

    Inventor： Sandip Tiwari ,  Chung Kim

    IPC: G11C11/34

    CPC classification number: H01L27/115 ,  B81B3/0072 ,  B81B2201/016 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/14 ,  G11C2213/17 ,  G11C2213/77 ,  H01H9/547 ,  H01H59/0009 ,  H01H61/0107 ,  H01L21/28273 ,  H01L27/112 ,  H01L29/66825 ,  H01L29/785

    Abstract: Mechanical devices having bistable positions are utilized to form switches and memory devices. The devices are actuatable to different positions and may be coupled to a transistor device in various configurations to provide memory devices. Actuation mechanisms include electrostatic methods and heat. In one form, the mechanical device forms a gate for a field effect transistor. In a further form, the device may be a switch that may be coupled to the transistor in various manners to affect its electrical characteristics when on and off. The memory switch in one embodiment comprises side walls formed with tensile or compressive films. A cross point switch is formed from a plurality of intersecting conductive rows and columns of conductors. Actuatable switches are positioned between each intersection of the rows and columns such that each intersection is independently addressable.

    Abstract translation: 利用具有双稳态位置的机械装置来形成开关和存储装置。 这些器件可被驱动到不同的位置，并且可以以各种配置耦合到晶体管器件以提供存储器件。 致动机制包括静电法和热量。 在一种形式中，机械装置形成用于场效应晶体管的栅极。 在另一种形式中，器件可以是开关，其可以以各种方式耦合到晶体管，以便在接通和断开时影响其电特性。 在一个实施例中的存储器开关包括由拉伸或压缩膜形成的侧壁。 交叉点开关由多个交叉的导电行和导体列形成。 可执行开关位于行和列的每个交叉点之间，使得每个交叉点可独立寻址。

    Scalable nano-transistor and memory using back-side trapping
    47.
    发明授权
    Scalable nano-transistor and memory using back-side trapping 有权
    可扩展的纳米晶体管和内存使用后端捕获

    公开(公告)号：US07057234B2

    公开(公告)日：2006-06-06

    申请号：US10462386

    申请日：2003-06-16

    Applicant: Sandip Tiwari

    Inventor： Sandip Tiwari

    IPC: H01L27/01

    CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L21/76254 ,  H01L27/10 ,  H01L29/66825

    Abstract: According to an aspect of the invention, a device structure is provided where charging and discharging occur in a trapping region formed by a stack of films that is placed on the back of a thin silicon channel. Uncoupling the charging mechanisms that lead to the memory function from the front gate transistor operation allows efficient scaling of the front gate. But significantly more important is a unique character of these devices: these structures can be operated both as a transistor and as a memory. The thin active silicon channel and the thin front oxide provide the capability of scaling the structure to tens of nanometers, and the dual function of the device is obtained by using two voltage ranges that are clearly distinct. At small voltages the structure operates as a normal transistor, and at higher voltages the structure operates as a memory device.

    Abstract translation: 根据本发明的一个方面，提供一种器件结构，其中充电和放电发生在由放置在薄硅通道的背面上的一叠薄膜形成的捕获区域中。 从前门晶体管操作中解除导致存储功能的充电机制允许前门的高效缩放。 但是，更重要的是这些器件的独特特性：这些结构可以作为晶体管和存储器运行。 薄的有源硅沟道和薄的前部氧化物提供了将结构缩放到几十纳米的能力，并且通过使用明显不同的两个电压范围来获得器件的双重功能。 在小电压下，结构作为正常晶体管工作，在较高电压下，该结构作为存储器件运行。

    Patterned SOI regions on semiconductor chips
    49.
    发明授权
    Patterned SOI regions on semiconductor chips 有权
    半导体芯片上的图案化SOI区域

    公开(公告)号：US06756257B2

    公开(公告)日：2004-06-29

    申请号：US09975435

    申请日：2001-10-11

    Applicant: Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

    Inventor： Bijan Davari ,  Devendra Kumar Sadana ,  Ghavam G. Shahidi ,  Sandip Tiwari

    IPC: H01L2100

    CPC classification number: H01L27/10894 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/76243 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76286 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/945 ,  Y10S257/904

    Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

    Abstract translation: 描述了用于形成图案化SOI区域和体积区域的方法和结构，其中绝缘体上的含硅层可以具有多个选定的厚度，并且其中体积区域可适于形成DRAM，并且SOI区域可适合于形成合并逻辑 如CMOS。 氧离子注入用于在所选择的深度形成图案化的掩埋氧化物层，并且掩模边缘可被成形为从一个深度到另一个深度形成阶梯状氧化物区域。 可以通过掩埋氧化物端部区域形成沟槽，以去除含有单晶硅的衬底中的高浓度位错。 本发明克服了形成DRAM的存储电容器形成的体积为Si的深沟槽，同时在SOI上形成合并的逻辑区域的问题。

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