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    Shape memory device
    1.
    发明申请
    Shape memory device 有权
    形状记忆装置

    公开(公告)号：US20070086237A1

    公开(公告)日：2007-04-19

    申请号：US11528712

    申请日：2006-09-27

    Applicant: Sandip Tiwari ,  Chung Kim

    Inventor： Sandip Tiwari ,  Chung Kim

    IPC: G11C11/34

    CPC classification number: H01L27/115 ,  B81B3/0072 ,  B81B2201/016 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  G11C13/025 ,  G11C23/00 ,  G11C2213/14 ,  G11C2213/17 ,  G11C2213/77 ,  H01H9/547 ,  H01H59/0009 ,  H01H61/0107 ,  H01L21/28273 ,  H01L27/112 ,  H01L29/66825 ,  H01L29/785

    Abstract: Mechanical devices having bistable positions are utilized to form switches and memory devices. The devices are actuatable to different positions and may be coupled to a transistor device in various configurations to provide memory devices. Actuation mechanisms include electrostatic methods and heat. In one form, the mechanical device forms a gate for a field effect transistor. In a further form, the device may be a switch that may be coupled to the transistor in various manners to affect its electrical characteristics when on and off. The memory switch in one embodiment comprises side walls formed with tensile or compressive films. A cross point switch is formed from a plurality of intersecting conductive rows and columns of conductors. Actuatable switches are positioned between each intersection of the rows and columns such that each intersection is independently addressable.

    Abstract translation: 利用具有双稳态位置的机械装置来形成开关和存储装置。 这些器件可被驱动到不同的位置，并且可以以各种配置耦合到晶体管器件以提供存储器件。 致动机制包括静电法和热量。 在一种形式中，机械装置形成用于场效应晶体管的栅极。 在另一种形式中，器件可以是开关，其可以以各种方式耦合到晶体管，以便在接通和断开时影响其电特性。 在一个实施例中的存储器开关包括由拉伸或压缩膜形成的侧壁。 交叉点开关由多个交叉的导电行和导体列形成。 可执行开关位于行和列的每个交叉点之间，使得每个交叉点可独立寻址。

    PHASE TRANSITION MEMORIES AND TRANSISTORS
    2.
    发明申请
    PHASE TRANSITION MEMORIES AND TRANSISTORS 有权
    相转移记忆和晶体管

    公开(公告)号：US20120280301A1

    公开(公告)日：2012-11-08

    申请号：US13322379

    申请日：2010-05-28

    Applicant: Sandip Tiwari ,  Ravishankar Sundararaman ,  Sang Hyeon Lee ,  Moonkyung Kim

    Inventor： Sandip Tiwari ,  Ravishankar Sundararaman ,  Sang Hyeon Lee ,  Moonkyung Kim

    IPC: H01L29/788 ,  H01L21/336

    CPC classification number: H01L29/685 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517

    Abstract: In one embodiment there is set forth a method comprising providing a semiconductor structure having an electrode, wherein the providing includes providing a phase transition material region and wherein the method further includes imparting energy to the phase transition material region to induce a phase transition of the phase transition material region. By inducing a phase transition of the phase transition material region, a state of the semiconductor structure can be changed. There is further set forth an apparatus comprising a structure including an electrode and a phase transition material region, wherein the apparatus is operative for imparting energy to the phase transition material region to induce a phase transition of the phase transition material region without the phase transition of the phase transition material region being dependent on electron transport through the phase transition material region.

    Abstract translation: 在一个实施例中，提出了一种方法，包括提供具有电极的半导体结构，其中所述提供包括提供相变材料区域，并且其中所述方法还包括赋予相变材料区域能量以引起相位的相变 过渡材料区域。 通过引起相变材料区域的相变，可以改变半导体结构的状态。 还提出了一种装置，其包括包括电极和相变材料区域的结构，其中该装置可操作以将能量传递给相变材料区域，以引起相变材料区域的相变而不发生相变 相变材料区域依赖于通过相变材料区域的电子传输。

    Electro-Mechanical Transistor
    3.
    发明申请
    Electro-Mechanical Transistor 有权
    机电晶体管

    公开(公告)号：US20110049650A1

    公开(公告)日：2011-03-03

    申请号：US12549906

    申请日：2009-08-28

    Applicant: Sandip Tiwari ,  Moon-Kyung Kim ,  Joshua Mark Rubin ,  Soo-Doo Chae ,  Choong-Man Lee ,  Ravishankar Sundararaman

    Inventor： Sandip Tiwari ,  Moon-Kyung Kim ,  Joshua Mark Rubin ,  Soo-Doo Chae ,  Choong-Man Lee ,  Ravishankar Sundararaman

    IPC: H01L29/84

    CPC classification number: H01L49/00 ,  B82Y10/00 ,  G11C13/025 ,  G11C23/00

    Abstract: An electromechanical transistor includes a source electrode and a drain electrode spaced apart from each other. A source pillar is between the substrate and the source electrode. A drain pillar is between the substrate and the drain electrode. A moveable channel is spaced apart from the source electrode and the drain electrode. A gate nano-pillar is between the moveable channel and the substrate. A first dielectric layer is between the moveable channel and the gate nano-pillar. A second dielectric layer is between the source pillar and the source electrode. A third dielectric layer is between the drain pillar and the drain electrode.

    Abstract translation: 机电晶体管包括彼此间隔开的源电极和漏电极。 源极柱位于衬底和源电极之间。 漏极柱位于衬底和漏电极之间。 可移动通道与源电极和漏电极间隔开。 门纳米柱位于可移动通道和基板之间。 第一电介质层位于可移动沟道和栅极纳米柱之间。 第二电介质层位于源极柱和源极之间。 第三介电层位于漏极柱和漏极之间。

    UHV horizontal hot wall cluster CVD/growth design
    4.
    发明授权
    UHV horizontal hot wall cluster CVD/growth design 失效
    特高压水平热壁簇CVD /生长设计

    公开(公告)号：US06350321B1

    公开(公告)日：2002-02-26

    申请号：US09207353

    申请日：1998-12-08

    Applicant: Kevin K. Chan ,  Christopher P. D'Emic ,  Raymond M. Sicina ,  Paul M. Kozlowski ,  Margaret Manny ,  Sandip Tiwari

    Inventor： Kevin K. Chan ,  Christopher P. D'Emic ,  Raymond M. Sicina ,  Paul M. Kozlowski ,  Margaret Manny ,  Sandip Tiwari

    IPC: C23C1600

    CPC classification number: H01L21/67225 ,  C23C14/56

    Abstract: A cluster system controls the interface properties of the films that deposit or grow on a silicon substrate. The system comprises a plurality of horizontal quartz chamber or tubes each of which can hold a large quantity of wafers, a transfer chamber and a load/unload chamber. Several process steps can be executed sequentially in different tubes without intermediate exposure to ambient air. A transfer chamber connects them and allows wafer transportation from one tube to another in an absolute controlled UHV environment which limits any contamination such as H2O, to less than a monolayer level. In addition, each tube can be pumped down to UHV pressure regime to avoid further cross contamination between tubes or particle generation. Since some of the process requires elevated temperature, all wafers are placed vertically on the quartz boat to prevent any wafer sagging as in a vertical furnace. Furthermore, before any wafers are placed into the transfer chamber, they are loaded into a load/unload chamber, which is the sole connection to the ambient air, to be purged and pumped so as to minimize particles and contamination.

    Abstract translation: 簇系统控制在硅衬底上沉积或生长的膜的界面性质。 该系统包括多个水平石英腔或管，每个水平的石英腔或管可以容纳大量的晶片，传送室和装载/卸载室。 可以在不同环境空气的情况下，在不同的管中顺序执行若干工艺步骤。 传输室连接它们，并允许晶片在绝对控制的特高压环境中从一个管到另一个管输送，将任何污染（例如H 2 O）限制到小于单层。 此外，每个管可以泵送到特高压压力状态，以避免管之间的进一步交叉污染或产生颗粒。 由于某些过程需要升高的温度，因此将所有晶片垂直放置在石英舟上，以防止垂直炉中出现任何晶片下垂。 此外，在将任何晶片放入转移室之前，它们被装载到与环境空气的唯一连接的装载/卸载室中，以被清除和泵送，以使颗粒和污染物最小化。

    Method for fabricating a gallium arsenide semiconductor device
    5.
    发明授权
    Method for fabricating a gallium arsenide semiconductor device 失效
    砷化镓半导体器件的制造方法

    公开(公告)号：US4558509A

    公开(公告)日：1985-12-17

    申请号：US626563

    申请日：1984-06-29

    Applicant: Sandip Tiwari

    Inventor： Sandip Tiwari

    IPC: H01L21/225 ,  H01L21/324 ,  H01L21/338 ,  H01L29/04 ,  H01L29/812 ,  H01L21/265 ,  H01L21/20

    CPC classification number: H01L29/045 ,  H01L21/2258 ,  H01L21/3245 ,  H01L29/812

    Abstract: A method for forming a FET in a gallium arsenide substrate whereby a gate is positioned on a [100] surface of the gallium arsenide substrate in the [011] orientation, active impurities are ion implanted to form FET source and drain regions which are self-aligned with respect to the gate, and the structure is annealed subsequent to the ion implanting whereby the active impurities are caused to diffuse laterally and thereby form channel region beneath the gate.

    Abstract translation: 一种用于在砷化镓衬底中形成FET的方法，其中栅极位于[011]取向的砷化镓衬底的[100]表面上，有源杂质被离子注入以形成FET源极和漏极区， 并且结构在离子注入之后被退火，由此使活性杂质横向扩散，从而形成栅极下方的沟道区域。

    Novel floating dosage form
    8.
    发明申请
    Novel floating dosage form 审中-公开
    新型漂浮剂型

    公开(公告)号：US20060013876A1

    公开(公告)日：2006-01-19

    申请号：US10518909

    申请日：2003-06-25

    Applicant: Braj Lohray ,  Sandip Tiwari ,  Raveendra Pai ,  Krishna Murthy ,  Pavak Mehta

    Inventor： Braj Lohray ,  Sandip Tiwari ,  Raveendra Pai ,  Krishna Murthy ,  Pavak Mehta

    IPC: A61K9/24

    CPC classification number: A61K9/0065

    Abstract: Present invention relates to a novel pharmaceutical composition containing an active ingredient(s) which is retained in the stomach or upper part of gastrointestinal tract for controlled delivery of medicament for improved local treatment, and/or better absorption from upper parts of gastrointestinal tract for effective therapeutic results. Present invention also provides a method for preparation of the said dosage form preferably in the form of a bilayer tablet, in which one layer constitutes for spatial control and the other being for temporal control.

    Abstract translation: 本发明涉及含有活性成分的新型药物组合物，其保留在胃或胃肠道上部，用于控制递送用于改善局部治疗的药物和/或从胃肠道上部更好地吸收以有效地 治疗结果。 本发明还提供了优选以双层片剂形式制备所述剂型的方法，其中一层构成用于空间控制，另一层构成用于时间控制。

    Floating back gate electrically erasable programmable read-only memory(EEPROM)
    9.
    发明授权
    Floating back gate electrically erasable programmable read-only memory(EEPROM) 失效
    浮动后门电可擦除可编程只读存储器（EEPROM）

    公开(公告)号：US06445032B1

    公开(公告)日：2002-09-03

    申请号：US09072293

    申请日：1998-05-04

    Applicant: Arvind Kumar ,  Sandip Tiwari

    Inventor： Arvind Kumar ,  Sandip Tiwari

    IPC: H01L29788

    CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/1203 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885

    Abstract: A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.

    Abstract translation: 一种半导体存储器和一种制造存储器的方法，包括：晶体管，包括具有氧化物的第一栅极和沟道，以及包括第二栅极和其上的氧化物的背面，与第二栅极 晶体管，第二栅极包括浮置栅极，其中背面的氧化物的厚度与晶体管的第一栅极的氧化物分开地可分级。

    Lateral trench optical detectors
    10.
    发明授权
    Lateral trench optical detectors 失效
    横向沟槽光学检测器

    公开(公告)号：US06177289B1

    公开(公告)日：2001-01-23

    申请号：US09205433

    申请日：1998-12-04

    Applicant: John Crow ,  Steve Koester ,  Daniel M. Kuchta ,  Dennis L. Rogers ,  Devendra Sadana ,  Sandip Tiwari

    Inventor： John Crow ,  Steve Koester ,  Daniel M. Kuchta ,  Dennis L. Rogers ,  Devendra Sadana ,  Sandip Tiwari

    IPC: H01L2166

    CPC classification number: H01L31/03529 ,  H01L31/035281 ,  H01L31/105 ,  Y02E10/50

    Abstract: A monolithic semiconductor optical detector is formed on a substrate having a plurality of substantially parallel trenches etched therein. The trenches are further formed as a plurality of alternating N-type and P-type trench regions separated by pillar regions of the substrate which operate as an I region between the N and P trench regions. First and second contacts are formed on the surface of the substrate and interconnect the N-type trench regions and the P-type trench regions, respectively. Preferably, the trenches are etched with a depth comparable to an optical extinction length of optical radiation to which the detector is responsive.

    Abstract translation: 单片半导体光检测器形成在其上蚀刻有多个基本上平行的沟槽的衬底上。 沟槽还形成为由作为N沟道区域和P沟道区域之间的I区域的基板的柱状区域分离的多个交替的N型和P型沟槽区域。 第一和第二触点形成在衬底的表面上并分别互连N型沟槽区和P型沟槽区。 优选地，以与检测器响应的光辐射的光消光长度相当的深度蚀刻沟槽。

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