公开(公告)号：US08536064B2

公开(公告)日：2013-09-17

申请号：US12701927

申请日：2010-02-08

申请人： Chung-Chi Ko ,  Chih-Hao Chen ,  Keng-Chu Lin

发明人： Chung-Chi Ko ,  Chih-Hao Chen ,  Keng-Chu Lin

IPC分类号： H01L21/302

CPC分类号： H01L21/31105 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76832

摘要： A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer.

公开(公告)号：US08481412B2

公开(公告)日：2013-07-09

申请号：US12893399

申请日：2010-09-29

申请人： Chung-Chi Ko ,  Chia Cheng Chou ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Shwang-Ming Jeng ,  Mei-Ling Chen

发明人： Chung-Chi Ko ,  Chia Cheng Chou ,  Keng-Chu Lin ,  Joung-Wei Liou ,  Shwang-Ming Jeng ,  Mei-Ling Chen

IPC分类号： H01L21/425

CPC分类号： H01L21/768 ,  H01L21/02126 ,  H01L21/02134 ,  H01L21/02137 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/70 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828

摘要： A method of and apparatus for forming interconnects on a substrate includes etching patterns in ultra-low k dielectric and removing moisture from the ultra-low k dielectric using active energy assist baking. During active energy assist baking, the ultra-low k dielectric is heated and exposed to light having only wavelengths greater than 400 nm for about 1 to about 20 minutes at a temperature of about 300 to about 400 degrees Celsius. The active energy assist baking is performed after wet-cleaning or after chemical mechanical polishing, or both.

摘要翻译： 用于在衬底上形成互连的方法和装置包括在超低k电介质中的蚀刻图案，并且使用主动能量辅助烘烤从超低k电介质去除湿气。 在活性能量辅助烘烤期间，在约300至约400摄氏度的温度下，超低k电介质被加热并暴露于仅具有大于400nm波长的光约1至约20分钟。 活性能量辅助烘烤在湿清洗或化学机械抛光之后进行，或两者都进行。

公开(公告)号：US20130052755A1

公开(公告)日：2013-02-28

申请号：US13219317

申请日：2011-08-26

申请人： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

发明人： Chia-Cheng Chou ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC分类号： H01L21/66

CPC分类号： H01L22/26 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76883 ,  H01L22/12 ,  H01L22/20

摘要： A method includes etching a low-k dielectric layer on a wafer to form an opening in the low-k dielectric layer. An amount of a detrimental substance in the wafer is measured to obtain a measurement result. Process conditions for baking the wafer are determined in response to the measurement result. The wafer is baked using the determined process conditions.

公开(公告)号：US08361900B2

公开(公告)日：2013-01-29

申请号：US12761805

申请日：2010-04-16

申请人： Shing-Chyang Pan ,  Han-Hsin Kuo ,  Chung-Chi Ko ,  Ching-Hua Hsieh

发明人： Shing-Chyang Pan ,  Han-Hsin Kuo ,  Chung-Chi Ko ,  Ching-Hua Hsieh

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76861 ,  H01L21/76867 ,  H01L21/76873 ,  H01L2221/1089

摘要： A copper interconnect includes a copper layer formed in a dielectric layer. A liner is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the liner and the dielectric layer. The barrier layer is a metal oxide.

摘要翻译： 铜互连包括在电介质层中形成的铜层。 在铜层和电介质层之间形成衬垫。 在衬垫和电介质层之间的边界处形成阻挡层。 阻挡层是金属氧化物。

公开(公告)号：US20110223759A1

公开(公告)日：2011-09-15

申请号：US12724229

申请日：2010-03-15

申请人： Kuan-Chen Wang ,  Po-Cheng Shih ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

发明人： Kuan-Chen Wang ,  Po-Cheng Shih ,  Chung-Chi Ko ,  Keng-Chu Lin ,  Shwang-Ming Jeng

IPC分类号： H01L21/768

CPC分类号： H01L23/53295 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO2). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.

摘要翻译： 在互连结构的形成中，在电介质层中形成金属特征。 使用前体和包含碳作为前体的碳源气体在金属特征和电介质层上形成蚀刻停止层（ESL）。 碳源气体不含二氧化碳（CO2）。 前体选自基本上由1-甲基硅烷（1MS），2-甲基硅烷（2MS），3-甲基硅烷（3MS），4-甲基硅烷（4MS）及其组合组成的组。

公开(公告)号：US20100120253A1

公开(公告)日：2010-05-13

申请号：US12547232

申请日：2009-08-25

申请人： Shwang-Ming Jeng ,  Kin-Weng Wang ,  Hsin-Yi Tsai ,  Keng-Chu Lin ,  Chung-Chi Ko

发明人： Shwang-Ming Jeng ,  Kin-Weng Wang ,  Hsin-Yi Tsai ,  Keng-Chu Lin ,  Chung-Chi Ko

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/76808 ,  H01L2221/1063

摘要： Methods for improving post etch in via or trench formation in semiconductor devices. A preferred embodiment comprises forming a re-capping layer over a dielectric film following an initial etch to form a feature in the dielectric film, followed by additional etch and etch back processing steps. The re-capping method provides protection for underlying films and prevents film damage post etch. Uniform feature profiles are maintained and critical dimension uniformity is obtained by use of the methods of the invention. The time dependent dielectric breakdown performance is increased.

摘要翻译： 用于改善半导体器件中的通孔或沟槽形成中的后蚀刻的方法。 优选实施例包括在初始蚀刻之后在电介质膜上形成覆盖层，以在电介质膜中形成特征，随后进行另外的蚀刻和回蚀处理步骤。 重新覆盖方法为底层膜提供保护，并防止蚀刻后的膜损伤。 通过使用本发明的方法维持均匀的特征轮廓并获得临界尺寸均匀性。 时间依赖介电击穿性能提高。

公开(公告)号：US07429542B2

公开(公告)日：2008-09-30

申请号：US11404020

申请日：2006-04-14

申请人： Chung-Chi Ko ,  Keng-Chu Lin ,  Tien-I Bao

发明人： Chung-Chi Ko ,  Keng-Chu Lin ,  Tien-I Bao

IPC分类号： H01L21/26

CPC分类号： H01L21/3105 ,  H01L21/31058 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76825

摘要： An UV treatment for making a low-k dielectric layer having improved properties in a damascene structure. A low-k dielectric layer in a damascene structure is subjected to an UV treatment with He gas or H2 gas to eliminate etching damage to the exposed surfaces of the low-k dielectric layer.

摘要翻译： 用于制造具有改进的镶嵌结构性能的低k电介质层的UV处理。 用Ho气体或H 2 O 2气体对镶嵌结构中的低k电介质层进行UV处理，以消除对低k电介质层的暴露表面的蚀刻损伤。

公开(公告)号：US07410895B2

公开(公告)日：2008-08-12

申请号：US11179265

申请日：2005-07-12

申请人： Keng-Chu Lin ,  Chung-Chi Ko ,  Yi-Chi Liao

发明人： Keng-Chu Lin ,  Chung-Chi Ko ,  Yi-Chi Liao

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76825

摘要： A method for forming an interconnect structure. A substrate is provided with a low-k dielectric layer thereon. At least one conductive feature is then formed in the low-k dielectric layer. A cap layer is formed overlying the low-k dielectric layer, and the conductive feature and the low-k dielectric layer is then subjected to an energy source to reduce a dielectric constant thereof.

摘要翻译： 一种形成互连结构的方法。 衬底上设置有低k电介质层。 然后在低k电介质层中形成至少一个导电特征。 形成覆盖低k电介质层的覆盖层，然后使导电特征和低k电介质层经受能量源以降低其介电常数。

公开(公告)号：US20070278682A1

公开(公告)日：2007-12-06

申请号：US11509498

申请日：2006-08-24

申请人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure of an integrated circuit includes a low-k dielectric layer over a semiconductor substrate, a conductor in the low-k dielectric layer, and a dielectric transition layer between the low-k dielectric layer and the conductor, wherein the dielectric transition layer has a thickness of less than about 50 Å.

摘要翻译： 集成电路的互连结构包括半导体衬底上的低k电介质层，低k电介质层中的导体和低k电介质层与导体之间的介电过渡层，其中介电转移层 具有小于约50埃的厚度。

公开(公告)号：US06908773B2

公开(公告)日：2005-06-21

申请号：US10102574

申请日：2002-03-19

申请人： Lain-Jong Li ,  Syun-Ming Jang ,  Chung-Chi Ko

发明人： Lain-Jong Li ,  Syun-Ming Jang ,  Chung-Chi Ko

IPC分类号： G01N21/35 ,  G01N21/55 ,  G01R31/26 ,  H01L21/66

CPC分类号： G01N21/35 ,  G01N21/3563 ,  G01N21/552 ,  G01N21/94 ,  G01N2021/3595

摘要： Attenuated total reflectance (ATR)-Fourier transform infrared (FTIR) metal surface cleanliness monitoring is disclosed. A metal surface of a semiconductor die is impinged with an infrared (IR) beam, such as can be accomplished by using an ATR technique. The IR beam as reflected by the metal surface is measured. For instance, an interferogram of the reflected IR beam may be measured. A Fourier transform of the interferogram may also be performed, in accordance with an FTIR technique. To determine whether the metal surface is contaminated, the IR beam as reflected is compared to a reference sample. For example, the Fourier transform of the interferogram may be compared to the reference sample. If there is deviation by more than a threshold, the metal surface may be concluded as being contaminated.

摘要翻译： 公开了衰减全反射（ATR） - 傅立叶变换红外（FTIR）金属表面清洁度监测。 半导体管芯的金属表面被红外（IR）光束照射，例如可以通过使用ATR技术来实现。 测量由金属表面反射的IR光束。 例如，可以测量反射的IR光束的干涉图。 干涉图的傅立叶变换也可以根据FTIR技术进行。 为了确定金属表面是否被污染，将反射的IR光束与参考样品进行比较。 例如，干涉图的傅立叶变换可以与参考样本进行比较。 如果偏差大于阈值，金属表面可能被认定为被污染。