公开(公告)号：US5654210A

公开(公告)日：1997-08-05

申请号：US434673

申请日：1995-05-04

Applicant: Sheldon Aronowitz ,  James Kimball

Inventor： Sheldon Aronowitz ,  James Kimball

IPC: H01L21/265

CPC classification number: H01L21/26506 ,  H01L21/26513

Abstract: Formation of a barrier region in a single crystal group IV semiconductor substrate at a predetermined spacing from a doped region in the substrate is described to prevent or inhibit migration of dopant materials from an adjacent doped region through the barrier region. By implantation of group IV materials into a semiconductor substrate to a predetermined depth in excess of the depth of a doped region, a barrier region can be created in the semiconductor to prevent migration of the dopants from the doped region through the barrier region. The treatment of the single crystal substrate with the group IV material is carried out at a dosage and energy level sufficient to provide such a barrier region in the semiconductor substrate, but insufficient to result in amorphization (destruction) of the single crystal lattice of the semiconductor substrate. In another embodiment, a similar barrier region may be formed in the semiconductor substrate but at a depth less than that of the doped region to inhibit migration of the dopant to the surface of the substrate. Such barrier regions may be formed in the substrate both above and below the doped region to inhibit migration of the dopant in the doped region in either direction.

Abstract translation: 描述了以与衬底中的掺杂区域预定间隔的单晶IV IV半导体衬底中的阻挡区域的形成，以防止或抑制掺杂剂材料通过阻挡区域从相邻掺杂区域的迁移。 通过将IV族材料注入到半导体衬底中至超过掺杂区域的深度的预定深度，可以在半导体中产生阻挡区域，以防止掺杂剂从掺杂区域迁移穿过阻挡区域。 用IV族材料处理单晶衬底以足以在半导体衬底中提供这种势垒区域的剂量和能级进行，但不足以导致半导体单晶晶格的非晶化（破坏） 基质。 在另一个实施例中，可以在半导体衬底中形成类似的阻挡区，但是深度小于掺杂区的深度，以抑制掺杂剂向衬底表面的迁移。 这样的阻挡区域可以在掺杂区域的上方和下方的衬底中形成，以抑制掺杂区域在任一方向上的迁移。

公开(公告)号：US5504016A

公开(公告)日：1996-04-02

申请号：US323605

申请日：1994-10-17

Applicant: Sheldon Aronowitz

Inventor： Sheldon Aronowitz

IPC: G06F17/50 ,  H01L21/265 ,  H01L21/22 ,  H01L21/66

CPC classification number: H01L21/26513 ,  G06F17/5018 ,  H01L21/26506

Abstract: The effect of dopant-dopant interaction on diffusion in silicon for a specific set of impurities is modeled. The first step in the modeling process involved quantum chemical calculations. The connection between the atomic scale results and macroscopic behavior was made through the medium for transmission of interactions between dopants. The molecular orbitals of the lattice system comprise that medium; consequently, interactions can be transmitted, with minimal reduction in magnitude, over separations of hundreds of lattice spacings. Macroscopically, additional flux components are generated that modify the conventional expression of Fick's second law. Detailed simulation of boron and phosphorus diffusion in germanium rich regions of silicon illustrate the power of this approach to successfully model and predict the complex behavior exhibited by a particular set of interacting dopant species.

Abstract translation: 模拟掺杂剂 - 掺杂剂相互作用对硅中扩散的影响。 建模过程的第一步涉及量子化学计算。 通过用于透射掺杂剂之间的相互作用的介质，进行原子尺度结果与宏观行为之间的连接。 晶格系统的分子轨道包括该介质; 因此，在数百个晶格间距的分离上，可以以最小的幅度减小来传输相互作用。 在宏观上，产生了修改Fick第二定律的常规表达式的额外的通量分量。 富硅富集区中硼和磷扩散的详细模拟说明了这种方法成功建模和预测了一组特定的相互作用掺杂物种呈现的复杂行为的功能。

公开(公告)号：US5298435A

公开(公告)日：1994-03-29

申请号：US939982

申请日：1992-09-03

Applicant: Sheldon Aronowitz ,  Courtney L. Hart ,  Sung T. Ahn

Inventor： Sheldon Aronowitz ,  Courtney L. Hart ,  Sung T. Ahn

IPC: H01L21/22 ,  H01L21/265 ,  H01L29/161

CPC classification number: H01L21/26506 ,  H01L21/22 ,  H01L29/161 ,  Y10S438/914 ,  Y10S438/938 ,  Y10S438/965

Abstract: A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.

Abstract translation: 提供了使用锗抑制硅中的掺杂剂扩散的方法。 锗分布在硅晶格中的取代位置，以形成两个锗区域，这两个区域插入在要引入掺杂剂的区域和掺杂剂被排除的区域之间，两个锗区域充当掺杂剂扩散势垒。

公开(公告)号：US5296386A

公开(公告)日：1994-03-22

申请号：US665465

申请日：1991-03-06

Applicant: Sheldon Aronowitz ,  Courtney Hart ,  Court Skinner

Inventor： Sheldon Aronowitz ,  Courtney Hart ,  Court Skinner

IPC: H01L21/265 ,  H01L21/285 ,  H01L21/316 ,  H01L21/336 ,  H01L29/161

CPC classification number: H01L29/66477 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/26506 ,  H01L21/28525 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/66568 ,  Y10S148/048 ,  Y10S148/082

Abstract: Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming the germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.

Abstract translation: 锗用于显着增强带硅衬底的N沟道和P沟道金属氧化物半导体（MOS）晶体管通道中少数载流子的漂移迁移率。 锗处理也用于增强MOS器件的源/漏接触电导。 公开了使用锗注入和湿氧化形成富锗界面层的方法，或通过分子束外延生长硅 - 锗合金。

公开(公告)号：US5043292A

公开(公告)日：1991-08-27

申请号：US531509

申请日：1990-05-31

Applicant: Sheldon Aronowitz ,  Courtney L. Hart ,  Matthew Buynoski

Inventor： Sheldon Aronowitz ,  Courtney L. Hart ,  Matthew Buynoski

IPC: H01L21/266 ,  H01L21/316 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L21/02238 ,  H01L21/02299 ,  H01L21/266 ,  H01L21/31662 ,  H01L21/74 ,  Y10S438/945 ,  Y10S438/95 ,  Y10S438/966

Abstract: A self-aligned masking process for use with ultra-high energy implants (implant energies equal to or greater than 1 MeV) is provided. The process can be applied to an arbitrary range of implant energies. Consequently, high doses of dopant may be implanted to give high concentrations that are deeply buried. This can be coupled with the fact that amorphization of the substrate lattice is relatively localized to the region where the ultra-high energy implant has peaked to yield a procedure to form buried, localized isolation structures.

公开(公告)号：US07829455B2

公开(公告)日：2010-11-09

申请号：US11104763

申请日：2005-04-12

Applicant: Vladimir Zubkov ,  Sheldon Aronowitz

Inventor： Vladimir Zubkov ,  Sheldon Aronowitz

IPC: H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76802

Abstract: A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the dielectric layer from the copper containing layer. The barrier layer comprises a silicon oxide layer and a dopant, where the dopant is a divalent ion, which dopes the silicon oxide layer adjacent to the copper containing layer.A method of forming a barrier layer is provided. A silicon oxide layer with a surface is provided. The surface of the silicon oxide layer is doped with a divalent ion to form a barrier layer extending to the surface of the silicon oxide layer. An electrically conductive copper containing layer is formed on the surface of the barrier layer, where the barrier layer prevents diffusion of copper into the substrate.

Abstract translation: 提供了一种用于半导体器件的阻挡层。 该半导体器件包括电介质层，导电含铜层和将电介质层与含铜层隔开的阻挡层。 阻挡层包括氧化硅层和掺杂剂，其中掺杂剂是二价离子，其掺杂与含铜层相邻的氧化硅层。 提供形成阻挡层的方法。 提供具有表面的氧化硅层。 氧化硅层的表面掺杂有二价离子以形成延伸到氧化硅层的表面的势垒层。 在阻挡层的表面上形成导电含铜层，其中阻挡层防止铜扩散到衬底中。

公开(公告)号：US07670645B1

公开(公告)日：2010-03-02

申请号：US11939482

申请日：2007-11-13

Applicant: Sheldon Aronowitz ,  James O. Kimball

Inventor： Sheldon Aronowitz ,  James O. Kimball

IPC: C23C16/06

CPC classification number: C23C14/18 ,  C23C14/228

Abstract: Techniques for vaporizing and handling a vaporized metallic element or metallic element salt with a heated inert carrier gas for further processing. The vaporized metallic element or salt is carried by an inert carrier gas heated to the same temperature as the vaporizing temperature to a heated processing chamber. The metal or salt vapor may be ionized (and implanted) or deposited on substrates. Apparatus for accomplishing these techniques, which include carrier gas heating chambers and heated processing chambers are also provided.

Abstract translation: 用加热的惰性载气汽化和处理蒸发的金属元素或金属元素盐进行进一步处理的技术。 蒸发的金属元素或盐由加热至与蒸发温度相同的温度的惰性载气携带到加热的处理室。 金属或盐蒸气可以离子化（和注入）或沉积在基底上。 还提供了用于实现这些技术的装置，其包括载气加热室和加热处理室。

公开(公告)号：US07115991B1

公开(公告)日：2006-10-03

申请号：US10044864

申请日：2001-10-22

Applicant: Vladimir Zubkov ,  Sheldon Aronowitz

Inventor： Vladimir Zubkov ,  Sheldon Aronowitz

IPC: H01L23/54

CPC classification number: H01L21/76831 ,  H01L21/76802

Abstract: A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the dielectric layer from the copper containing layer. The barrier layer comprises a silicon oxide layer and a dopant, where the dopant is a divalent ion, which dopes the silicon oxide layer adjacent to the copper containing layer.A method of forming a barrier layer is provided. A silicon oxide layer with a surface is provided. The surface of the silicon oxide layer is doped with a divalent ion to form a barrier layer extending to the surface of the silicon oxide layer. An electrically conductive copper containing layer is formed on the surface of the barrier layer, where the barrier layer prevents diffusion of copper into the substrate.

Abstract translation: 提供了一种用于半导体器件的阻挡层。 该半导体器件包括电介质层，导电含铜层和将电介质层与含铜层隔开的阻挡层。 阻挡层包括氧化硅层和掺杂剂，其中掺杂剂是二价离子，其掺杂与含铜层相邻的氧化硅层。 提供形成阻挡层的方法。 提供具有表面的氧化硅层。 氧化硅层的表面掺杂有二价离子以形成延伸到氧化硅层的表面的势垒层。 在阻挡层的表面上形成导电含铜层，其中阻挡层防止铜扩散到衬底中。

公开(公告)号：US07015168B2

公开(公告)日：2006-03-21

申请号：US10652007

申请日：2003-08-29

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov

IPC: C04B35/14 ,  H01L21/31 ,  H01L23/58

CPC classification number: H01L21/02126 ,  C01B33/126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/3121 ,  H01L21/31629 ,  H01L21/31633 ,  Y02P20/129

Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R3R4, where: (a) R1 is selected from H, a 3 to 10 carbon alkyl, and an alkoxy; (b) R2 contains at least one C atom bonded to at least one F atom, and no aliphatic C—H bonds; and (c) R3 and R4 are selected from H, alkyl, alkoxy, a moiety containing at least one C atom bonded to at least one F atom, and ((L)Si(R5)(R6))n(R7); where n ranges from 1 to 10; L is O or CFR8; each n R5 and R6 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; R7 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; and each R8 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom. Also provided is a low dielectric constant fluorine and carbon-doped silicon oxide dielectric material for use in an integrated circuit structure which contains: silicon atoms bonded to oxygen atoms; silicon atoms bonded to carbon atoms; and carbon atoms bonded to fluorine atoms; where the dielectric material also has a characteristic selected from: (a) the presence of at least one C—C bond; (b) the presence of at least one carbon atom bonded to from 1 to 2 fluorine atoms; and (c) the presence of at least one silicon atom bonded to from 0 to 2 oxygen atoms.

公开(公告)号：US20050258475A1

公开(公告)日：2005-11-24

申请号：US11189625

申请日：2005-07-25

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace Sun

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace Sun

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L29/513 ,  H01L29/78

Abstract: An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.

Abstract translation: 公开了一种改进的半导体存储器结构及其制造方法。 存储器结构包括具有在半导体衬底的沟道区上形成的电介质叠层的半导体衬底。 电介质堆叠包括作为存储器件的电荷存储中心工作的电子俘获材料层。 栅电极与电介质叠层的顶部连接。 在各种实施例中，电子捕获材料形成介电叠层的更大或更小的部分。 本发明包括用于形成这种存储器件的方法实施例。