公开(公告)号：US07202538B1

公开(公告)日：2007-04-10

申请号：US10647604

申请日：2003-08-25

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

IPC: H01L29/94

CPC classification number: H01L29/4238 ,  H01L21/28123 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/0692

Abstract: A MOSFET transistor structure is formed in a substrate of semiconductor material having a first conductivity type. The MOSFET transistor structure includes an active region that is surrounded by a perimeter isolation dielectric material formed in the substrate to define a continuous sidewall interface between the sidewall dielectric material and the active region. Spaced-apart source and drain regions are formed in the active region and are also spaced-apart from the sidewall interface. A conductive gate electrode that is separated from the substrate channel region by intervening gate dielectric material includes a first portion that extends over the substrate channel region and a second portion that extends continuously over the entire sidewall interface between the isolation dielectric material and the active region. Thus, an enclosed ring is maintained around the entire composite perimeter, thereby completely avoiding regions of high trap density and, thus, preventing any current path for gate induced drain leakage (GIDL) to occur.

Abstract translation: 在具有第一导电类型的半导体材料的衬底中形成MOSFET晶体管结构。 MOSFET晶体管结构包括由形成在衬底中的周边隔离电介质材料围绕以限定侧壁电介质材料和有源区域之间的连续侧壁界面的有源区域。 间隔开的源极和漏极区域形成在有源区中并且也与侧壁界面间隔开。 通过介入栅极电介质材料与衬底沟道区分离的导电栅电极包括在衬底沟道区上延伸的第一部分和在隔离电介质材料与有源区之间的整个侧壁界面上连续延伸的第二部分。 因此，围绕整个复合材料周边保持封闭的环，从而完全避免高陷阱密度的区域，并因此防止发生栅极引起漏极泄漏（GIDL）的任何电流路径。

公开(公告)号：US07180379B1

公开(公告)日：2007-02-20

申请号：US10838485

申请日：2004-05-03

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Yuri Mirgorodski

IPC: G01N21/00

CPC classification number: G06F1/105

Abstract: A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents which are sufficient to cause a logic inverter to switch states.

Abstract translation: 通过将每个本地时钟电路中的光电导区域暴露于以固定频率工作的脉冲光源，同时在多个本地时钟电路中产生同步时钟信号。 光电导区产生足以导致逻辑逆变器切换状态的光电流。

公开(公告)号：US20060266925A1

公开(公告)日：2006-11-30

申请号：US11496951

申请日：2006-08-01

Applicant: Peter Hopper ,  Philipp Lindorfer ,  Mark Poulter ,  Yuri Mirgorodski

Inventor： Peter Hopper ,  Philipp Lindorfer ,  Mark Poulter ,  Yuri Mirgorodski

IPC: H01L27/00

CPC classification number: H01L27/14609 ,  H04N5/35572 ,  H04N5/361 ,  H04N5/37452

Abstract: An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.

公开(公告)号：US06940133B1

公开(公告)日：2005-09-06

申请号：US10818039

申请日：2004-04-05

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Robert Drury

IPC: H01C17/26 ,  H01L21/02 ,  H01L29/76 ,  H01L29/8605 ,  H01L29/94

CPC classification number: H01L28/20 ,  H01C17/267 ,  H01L29/8605

Abstract: An integrated circuit trim structure includes a dopant source, a target trim element formed in proximity to the dopant source, and a conductive heating element. The heater element is formed in proximity to the dopant source and includes first and second terminals and a trapezoid shaped region formed between the first and second terminals. As predefined current pulse is applied to the first terminal to promote current flow between the first and second terminals, a local heat source is created at a predefined location within the trapezoid shaped region and in proximity to the dopant source such that dopant flows from the dopant source into the target trim element to change the conductive characteristics of the target trim element.

Abstract translation: 集成电路微调结构包括掺杂剂源，在掺杂剂源附近形成的目标微调元件和导电加热元件。 加热器元件形成在掺杂剂源附近，并且包括形成在第一和第二端子之间的第一和第二端子和梯形区域。 当预定义的电流脉冲施加到第一端子以促进第一和第二端子之间的电流流动时，在梯形区域内的预定位置处并且在掺杂剂源附近产生局部热源，使得掺杂剂从掺杂剂 源到目标装饰元件以改变目标装饰元件的导电特性。

公开(公告)号：US06933562B1

公开(公告)日：2005-08-23

申请号：US10609191

申请日：2003-06-27

Applicant: Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Andy Strachan

Inventor： Peter J. Hopper ,  Philipp Lindorfer ,  Vladislav Vashchenko ,  Andy Strachan

IPC: H01L23/482 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/94 ,  H01L31/113 ,  H01L31/119 ,  H01L29/46 ,  H01L31/62

CPC classification number: H01L29/41758 ,  H01L23/4824 ,  H01L29/0692 ,  H01L29/41725 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maximize the overall current carrying capacity of power transistor structure.

Abstract translation: 功率晶体管结构使用具有不均匀宽度的金属漏极和源极条来减小跨越功率晶体管结构的电流密度的变化。 电流密度的降低又降低了源极到漏极导通电阻，并使功率晶体管结构的总载流能力最大化。

公开(公告)号：US06924167B1

公开(公告)日：2005-08-02

申请号：US10438482

申请日：2003-05-15

Applicant: Peter J. Hopper ,  Philipp Lindorfer

Inventor： Peter J. Hopper ,  Philipp Lindorfer

IPC: H01L27/146 ,  H04N3/15 ,  H04N9/04 ,  H01L21/00

CPC classification number: H04N9/045 ,  H01L27/14647 ,  H04N5/3696

Abstract: A combination of materials is used to form the photodiodes of a vertical color imager cell. The materials used to form the photodiodes have different band gaps that allow the photon absorption rates of the photodiodes to be adjusted. By adjusting the photon absorption rates, the sensitivities of the photodiodes and thereby the characteristics of the imager can be adjusted.

Abstract translation: 使用材料的组合来形成垂直彩色成像器单元的光电二极管。 用于形成光电二极管的材料具有不同的带隙，允许调整光电二极管的光子吸收速率。 通过调整光子吸收率，可以调节光电二极管的灵敏度，从而调整成像器的特性。

公开(公告)号：US06797555B1

公开(公告)日：2004-09-28

申请号：US10659422

申请日：2003-09-10

Applicant: Peter J. Hopper ,  Prasad Chaparala ,  Philipp Lindorfer ,  Vladislav Vashchenko

Inventor： Peter J. Hopper ,  Prasad Chaparala ,  Philipp Lindorfer ,  Vladislav Vashchenko

IPC: H01L218238

CPC classification number: H01L29/51 ,  H01L21/26506 ,  H01L29/1033

Abstract: Fluorine is implanted directly into the channel region of a PMOS transistor structure, thereby improving the noise and VT drift margin of device performance by introducing Si—F complexes at the substrate-gate oxide interface.

Abstract translation: 氟直接注入PMOS晶体管结构的沟道区，从而通过在衬底 - 栅极氧化物界面引入Si-F络合物来改善器件性能的噪声和VT漂移裕度。

公开(公告)号：US06720592B1

公开(公告)日：2004-04-13

申请号：US09895803

申请日：2001-06-29

Applicant: Willem Johannes Kindt ,  Philipp Lindorfer

Inventor： Willem Johannes Kindt ,  Philipp Lindorfer

IPC: H01L27148

CPC classification number: H01L27/14601

Abstract: The present invention is directed to a photogate based pixel cell with an electronic shutter and which provides relatively low lag and high sensitivity for sensing infrared light reflected from objects. Additionally, this invention eliminates the need for a transfer gate in the pixel cell. In one embodiment, the reset and shutter transistors are implemented with PMOS transistors so that the pixel cell can have an increased dynamic range and a relatively high voltage swing. In another embodiment, the actual size of each pixel cell can be further reduced when the reset gate and the electronic shutter are implemented with NMOS transistors. Also, when a P− well is not disposed beneath the photogate, the ability of the pixel cell to sense infrared light is improved. Correlated double sampling can be used to improve the accuracy of the signal read out from the pixel cell.

Abstract translation: 本发明涉及一种具有电子快门的基于光栅的像素单元，其提供用于感测从物体反射的红外光的相对较低的滞后和高灵敏度。 另外，本发明消除了对像素单元中的传输门的需要。 在一个实施例中，复位和快门晶体管由PMOS晶体管实现，使得像素单元可以具有增加的动态范围和相对高的电压摆幅。 在另一个实施例中，当复位门和电子快门用NMOS晶体管实现时，可以进一步减小每个像素单元的实际尺寸。 此外，当P-阱不设置在光栅下方时，像素单元感测红外光的能力得到改善。 可以使用相关的双重采样来提高从像素单元读出的信号的精度。

公开(公告)号：US06707117B1

公开(公告)日：2004-03-16

申请号：US10285235

申请日：2002-10-31

Applicant: Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer ,  Andy Strachon ,  Peter Johnson

Inventor： Vladislav Vashchenko ,  Peter J. Hopper ,  Philipp Lindorfer ,  Andy Strachon ,  Peter Johnson

IPC: H01C2976

CPC classification number: H01L21/28518 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor structure, interconnects between regions of a single device or different devices are achieved by forming metal plugs that span across the regions to be interconnected, wherein the plugs are formed from the metal used in forming a silicide layer on the structure. The metal is masked off in desired areas prior to etching, to leave the metal plugs.

Abstract translation: 在半导体结构中，单个器件或不同器件的区域之间的互连通过形成跨越要互连的区域的金属插塞来实现，其中插塞由在结构上形成硅化物层所用的金属形成。 在蚀刻之前，将金属掩盖在所需区域中，以留下金属塞。

公开(公告)号：US06534759B1

公开(公告)日：2003-03-18

申请号：US09950121

申请日：2001-09-10

Applicant: Waclaw C. Koscielniak ,  Philipp Lindorfer

Inventor： Waclaw C. Koscielniak ,  Philipp Lindorfer

IPC: H01L3100

CPC classification number: H01L27/14645 ,  H01L31/101 ,  H01L31/103 ,  H01L31/18

Abstract: A vertical photodetector for detecting different wavelengths of light. The structure provides doped regions, which are separated by barrier regions. The doped regions detect photons corresponding to different wavelengths of light. Specifically, by detecting the amount of electrical charge collected by diodes positioned in the different doped regions, different wavelengths of light can be detected. The barrier regions inhibit the flow of electrical charges from one doped region into another doped region. The area of the doped regions can be increased, without increasing the capacitance of the diodes which are used to detect the electrical charges generated by light incident of the vertical photodetector.

Abstract translation: 用于检测不同波长的光的垂直光电探测器。 该结构提供掺杂区域，其被屏障区域分隔开。 掺杂区域检测对应于不同波长的光的光子。 具体地，通过检测位于不同掺杂区域中的二极管收集的电荷量，可以检测不同波长的光。 阻挡区域阻止电荷从一个掺杂区域流入另一个掺杂区域。 可以增加掺杂区域的面积，而不增加用于检测由垂直光电检测器入射的光产生的电荷的二极管的电容。