公开(公告)号：US20090161462A1

公开(公告)日：2009-06-25

申请号：US11963508

申请日：2007-12-21

申请人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

发明人： Sung-Yong Chung ,  Zhizheng Liu ,  Yugi Mizuguchi ,  Xuguang Alan Wang ,  Yi He ,  Ming Kwan ,  Darlene Hamilton ,  Sung-Chul Lee ,  Guowei Wang ,  Nancy Leong

IPC分类号： G11C7/02

CPC分类号： G11C16/3418 ,  G11C16/0416 ,  G11C16/24 ,  G11C16/3427

摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

摘要翻译： 提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。 在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。 可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。 该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。 这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

公开(公告)号：US20080150006A1

公开(公告)日：2008-06-26

申请号：US11724726

申请日：2007-03-16

申请人： Ming-Sang Kwan ,  Bradley Marc Davis ,  Jean Yee-Mei Yang ,  Zhizheng Liu ,  Yi He

发明人： Ming-Sang Kwan ,  Bradley Marc Davis ,  Jean Yee-Mei Yang ,  Zhizheng Liu ,  Yi He

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

摘要： The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.

摘要翻译： 本发明涉及在形成基于晶体管的存储器件中实现双重聚合工艺。 该过程允许在沉积第二多晶硅层之后选择性地掺杂第一多晶硅层。 该掺杂增加了第一多晶硅层的导电性，其可以实现针对多位磁芯阵列的更强鲁棒的充电保护和更均匀的电荷分布。

公开(公告)号：US07215577B2

公开(公告)日：2007-05-08

申请号：US11511763

申请日：2006-08-29

申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

IPC分类号： G11C11/34 ,  G11C16/04 ,  H01L29/78

CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

摘要翻译： 提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。 可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。 电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。 可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池 ，其中栅极电压电位高于衬底电压电位。

公开(公告)号：US06934190B1

公开(公告)日：2005-08-23

申请号：US10863933

申请日：2004-06-09

申请人： Zengtao Liu ,  Zhizheng Liu ,  Yi He ,  Sameer Haddad ,  Mark Randolph

发明人： Zengtao Liu ,  Zhizheng Liu ,  Yi He ,  Sameer Haddad ,  Mark Randolph

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C16/3454

摘要： Methods of operating dual bit memory devices including programming with a range of values are provided. The present invention employs a range of ramp source program pulses to iteratively perform a program operation that employs hot hole injection. The range is related to channel lengths of individual dual bit memory cells within the memory device. To program a bit of a particular dual bit memory cell, a negative gate program voltage is applied to its gate, a positive drain voltage is applied to its acting drain, and its substrate is connected to ground. Additionally, a ramp source voltage of the range of ramp source program pulses is concurrently applied to an acting source of the dual bit memory cell. A verification operation is then performed and the programming is repeated with a decremented ramp source voltage on verification failure.

摘要翻译： 提供了包括具有一定范围值的编程的双位存储器件的操作方法。 本发明采用一系列斜坡源程序脉冲来迭代地执行采用热空穴注入的程序操作。 该范围与存储器件内的各个双位存储单元的通道长度有关。 为了编程一个特定的双位存储单元，负栅极编程电压被施加到其栅极，正的漏极电压被施加到其作用漏极，并且其衬底连接到地。 此外，斜坡源程序脉冲范围的斜坡源电压同时施加到双位存储单元的作用源。 然后执行验证操作，并且在验证失败时以递减的斜坡源电压重复编程。

公开(公告)号：US06834012B1

公开(公告)日：2004-12-21

申请号：US10863673

申请日：2004-06-08

申请人： Yi He ,  Edward Franklin Runnion ,  Zhizheng Liu ,  Zengtao Liu ,  Mark William Randolph

发明人： Yi He ,  Edward Franklin Runnion ,  Zhizheng Liu ,  Zengtao Liu ,  Mark William Randolph

IPC分类号： G11C1604

CPC分类号： G11C16/3404 ,  G11C16/0475

摘要： Methods of operating dual bit flash memory devices and correcting over-erased dual bit flash memory devices are provided. The present invention includes a corrective action that employs a negative gate to correct over-erased memory cells without substantially altering threshold voltage values or charge states for properly erased memory cells. The negative gate stress is performed as a block operation by applying a negative gate voltage to gates and connecting active regions and a substrate to ground.

摘要翻译： 提供了操作双位闪存器件和校正过擦除的双位闪存器件的方法。 本发明包括采用负栅极来校正过擦除的存储单元而没有基本上改变正确擦除的存储单元的阈值电压值或电荷状态的校正动作。 通过向栅极施加负栅极电压并将有源区域和衬底连接到地来执行负栅极应力作为块操作。

公开(公告)号：US06958272B2

公开(公告)日：2005-10-25

申请号：US10755740

申请日：2004-01-12

申请人： Emmanuil H. Lingunis ,  Nga-Ching Alan Wong ,  Sameer Haddad ,  Mark W. Randolph ,  Mark T. Ramsbey ,  Ashot Melik-Martirosian ,  Edward F. Runnion ,  Yi He

发明人： Emmanuil H. Lingunis ,  Nga-Ching Alan Wong ,  Sameer Haddad ,  Mark W. Randolph ,  Mark T. Ramsbey ,  Ashot Melik-Martirosian ,  Edward F. Runnion ,  Yi He

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

摘要翻译： 公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。 最初，电荷俘获电介质层的一部分形成在衬底上，并且在电荷俘获电介质层的部分上形成抗蚀剂。 抗蚀剂被图案化，并且以一定角度执行凹穴注入以在衬底内建立口袋植入物。 然后执行位线注入以在衬底内建立掩埋位线。 然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层。 在剩余的电荷俘获电介质层中形成字线材料，并且被图案化以形成覆盖在位线上的字线。 口袋种植体用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。 因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

公开(公告)号：US06436768B1

公开(公告)日：2002-08-20

申请号：US09893279

申请日：2001-06-27

申请人： Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Emmanuil Manos Lingunis ,  Yider Wu ,  Tazrien Kamal ,  Yi He ,  Edward Hsia ,  Hidehiko Shiraiwa

发明人： Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Emmanuil Manos Lingunis ,  Yider Wu ,  Tazrien Kamal ,  Yi He ,  Edward Hsia ,  Hidehiko Shiraiwa

IPC分类号： H01L21336

CPC分类号： H01L21/2652 ,  H01L21/2658 ,  H01L27/11568 ,  H01L29/66833

摘要： One aspect of the present invention relates to a method of forming a SONOS type non-volatile semiconductor memory device, involving forming a first layer of a charge trapping dielectric on a semiconductor substrate; forming a second layer of the charge trapping dielectric over the first layer of the charge trapping dielectric on the semiconductor substrate; optionally at least partially forming a third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; forming a source/drain mask over the charge trapping dielectric; implanting a source/drain implant through the charge trapping dielectric into the semiconductor substrate; optionally removing the third layer of the charge trapping dielectric; and one of forming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, reforming the third layer of the charge trapping dielectric over the second layer of the charge trapping dielectric on the semiconductor substrate, or forming additional material over the third layer of the charge trapping dielectric.

摘要翻译： 本发明的一个方面涉及一种形成SONOS型非易失性半导体存储器件的方法，包括在半导体衬底上形成电荷俘获电介质的第一层; 在所述半导体衬底上的所述电荷俘获电介质的所述第一层上形成所述电荷俘获电介质的第二层; 可选地至少部分地在所述半导体衬底上的所述电荷俘获电介质的所述第二层上形成所述电荷俘获电介质的第三层; 任选地去除电荷俘获电介质的第三层; 在电荷俘获电介质上形成源极/漏极掩模; 将源极/漏极注入物通过电荷俘获电介质注入到半导体衬底中; 任选地去除电荷俘获电介质的第三层; 以及在半导体衬底上的电荷俘获电介质的第二层上形成电荷俘获电介质的第三层之一，在半导体衬底上的电荷俘获电介质的第二层上重整第三层电荷俘获电介质，或 在电荷俘获电介质的第三层上形成附加材料。

公开(公告)号：US08652582B2

公开(公告)日：2014-02-18

申请号：US12937458

申请日：2009-05-26

申请人： Catherine A. Bothof ,  Yi He ,  Jerald K. Rasmussen ,  Kannan Seshadri ,  Clinton P. Waller, Jr. ,  Douglas E. Weiss

发明人： Catherine A. Bothof ,  Yi He ,  Jerald K. Rasmussen ,  Kannan Seshadri ,  Clinton P. Waller, Jr. ,  Douglas E. Weiss

IPC分类号： C08F2/46

CPC分类号： C07C279/12 ,  B01D39/1676 ,  B01J20/285 ,  C07C277/08 ,  C07C279/14 ,  C07C281/16 ,  C07K1/34 ,  C08F259/08 ,  C08F283/04 ,  C08G69/48 ,  C08J7/18 ,  C08J9/283 ,  C08J9/42 ,  C08J2327/16 ,  C08J2377/00 ,  C12N7/00 ,  Y02C10/08 ,  Y10T428/31855

摘要： Ligand functionalized substrates, methods of making ligand functionalized substrates, and methods of using functionalized substrates are disclosed. The ligand functionalized substrate may be described as the grafted reaction product of a substrate and a ligand monomer of Formula I:

摘要翻译： 配体功能化底物，制备配体官能化底物的方法，以及使用官能化底物的方法。 配体官能化底物可以描述为底物和式I的配体单体的接枝反应产物：

公开(公告)号：US08497353B2

公开(公告)日：2013-07-30

申请号：US12867078

申请日：2009-02-12

申请人： Stephen B. Roscoe ,  Stephanie J. Moeller ,  Yi He ,  Richard B. Ross

发明人： Stephen B. Roscoe ,  Stephanie J. Moeller ,  Yi He ,  Richard B. Ross

IPC分类号： A61K38/16

CPC分类号： G01N33/56961 ,  C07K7/08 ,  G01N2469/10

摘要： Polypeptides which can be activated to cause the formation of pores in a lipid membrane are disclosed. Also disclosed are polypeptide compositions for the detection of target microorganisms and methods of using said compositions.

公开(公告)号：US08102679B2

公开(公告)日：2012-01-24

申请号：US12192399

申请日：2008-08-15

申请人： Xiaowu Gong ,  Siu Kam Kok ,  Yi He ,  Tuck Meng Chan

发明人： Xiaowu Gong ,  Siu Kam Kok ,  Yi He ,  Tuck Meng Chan

IPC分类号： H02M3/335

CPC分类号： H02M3/156 ,  H02M3/33507 ,  H02M2001/0022 ,  H02M2001/0032 ,  Y02B70/16

摘要： An embodiment of the invention relates to a power converter including a resistor divider with an internal node to sense an input line voltage. The internal node is operable as a multifunctional pin. A controller compares a feedback voltage dependent on a power converter output characteristic to a current-sense signal including an offset dependent on a voltage of the internal node to control entry and exit of the power converter from burst mode operation. The node may be employed to manage power converter operation by sensing or controlling its voltage to signal operation in a standby or burst mode, to sense the input line voltage, to enable an external system to signal shutdown to the power converter, and to enable the power converter to signal a delayed restart condition to the external system.

摘要翻译： 本发明的实施例涉及一种功率转换器，其包括具有用于感测输入线电压的内部节点的电阻分压器。 内部节点可用作多功能引脚。 控制器将取决于功率转换器输出特性的反馈电压与包括取决于内部节点的电压的偏移的电流检测信号进行比较，以控制功率转换器的进入和退出以进行突发模式操作。 可以采用该节点来管理功率转换器的操作，通过感测或控制其电压以在备用或突发模式下信号操作，以感测输入线路电压，使外部系统能够向功率转换器发出信号关闭， 电源转换器向外部系统发出延迟重启状态信号。