公开(公告)号：US06998666B2

公开(公告)日：2006-02-14

申请号：US10707754

申请日：2004-01-09

申请人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

发明人： Jochen Beintner ,  Rama Divakaruni ,  Rajarao Jammy

IPC分类号： H01L21/8242

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10894

摘要： A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate conductor and a boron-doped channel. The method includes forming trenches adjacent the DRAM cell and a silicon-oxy-nitride isolation liner on either side of the DRAM cell, adjacent the gate conductor. Isolation regions are then formed in the trenches on either side of the DRAM cell. Thereafter, the DRAM cell, including the boron-containing channel region adjacent the gate conductor, is subjected to elevated temperatures by thermal processing, for example, forming a support device on the substrate adjacent the isolation regions. The nitride-containing isolation liner reduces segregation of the boron in the channel region, as compared to an essentially nitrogen-free oxide-containing isolation liner.

摘要翻译： 一种制造集成电路器件的方法包括蚀刻衬底中的沟槽并形成具有位于下端的存储电容器的动态随机存取存储器（DRAM）单元和覆盖的垂直金属氧化物半导体场效应晶体管（MOSFET），其包括栅极 导体和掺硼通道。 该方法包括在DRAM单元附近形成沟槽和在DRAM单元的任一侧上与栅极导体相邻的硅 - 氮氧化物隔离衬垫。 然后在DRAM单元的两侧的沟槽中形成隔离区。 此后，包括与栅极导体相邻的含硼沟道区域的DRAM单元通过热处理受到升高的温度，例如，在邻近隔离区域的衬底上形成支撑器件。 与基本上不含氮氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中的硼的偏析。

公开(公告)号：US06869860B2

公开(公告)日：2005-03-22

申请号：US10250092

申请日：2003-06-03

申请人： Michael P. Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth T. Settlemeyer, Jr. ,  Padraic C. Shafer

发明人： Michael P. Belyansky ,  Rama Divakaruni ,  Laertis Economikos ,  Rajarao Jammy ,  Kenneth T. Settlemeyer, Jr. ,  Padraic C. Shafer

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76229

摘要： Isolation trenches and capacitor trenches containing vertical FETs (or any prior levels p-n junctions or dissimilar material interfaces) having an aspect ratio up to 60 are filled with a process comprising: applying a spin-on material based on silazane and having a low molecular weight; pre-baking the applied material in an oxygen ambient at a temperature below about 450 deg C.; converting the stress in the material by heating at an intermediate temperature between 450 deg C. and 800 deg C. in an H2O ambient; and heating again at an elevated temperature in an O2 ambient, resulting in a material that is stable up to 1000 deg C., has a compressive stress that may be tuned by variation of the process parameters, has an etch rate comparable to oxide dielectric formed by HDP techniques, and is durable enough to withstand CMP polishing.

摘要翻译： 包含具有高达60的纵横比的垂直FET（或任何先前级别的p-n结或异种材料界面）的隔离沟槽和电容器沟槽被填充了一种方法，其包括：施加基于硅氮烷并且具有低分子量的旋涂材料; 在低于约450℃的温度下在氧环境中预烘烤施加的材料; 通过在H 2 O环境中在450摄氏度和800摄氏度之间的中间温度下加热来转化材料中的应力; 并且在高温下再次在O 2环境中加热，得到稳定至高达1000℃的材料，具有可通过工艺参数变化调节的压缩应力，具有与形成的氧化物电介质相当的蚀刻速率 通过HDP技术，并且耐用性足以承受CMP抛光。

公开(公告)号：US06794706B2

公开(公告)日：2004-09-21

申请号：US10064493

申请日：2002-07-22

申请人： Fen Chen ,  Rajarao Jammy ,  Baozhen Li ,  Sebastian T. Ventrone

发明人： Fen Chen ,  Rajarao Jammy ,  Baozhen Li ,  Sebastian T. Ventrone

IPC分类号： H01L2976

CPC分类号： H01L21/28185 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02326 ,  H01L21/28194 ,  H01L21/3144 ,  H01L28/40 ,  H01L29/513 ,  H01L29/518 ,  H01L29/94

摘要： A capacitor structure having a re-oxide layer on a nitride layer, wherein an interface between the nitride layer and the re-oxide layer includes electron traps. Characteristics of the carrier traps control a voltage output of the device. The thickness of the nitride layer and the re-oxide layer also control the voltage output. The nitride layer and a re-oxide layer form a dielectric capacitor. The dielectric capacitor undergoes a trap filled limit voltage, wherein a consistent voltage is output for a plurality of currents.

摘要翻译： 一种在氮化物层上具有再氧化物层的电容器结构，其中氮化物层和再氧化物层之间的界面包括电子阱。 载波阱的特性控制器件的电压输出。 氮化物层和再氧化物层的厚度也控制电压输出。 氮化物层和再氧化物层形成介质电容器。 介质电容器经历陷阱填充极限电压，其中为多个电流输出一致的电压。

公开(公告)号：US06764551B2

公开(公告)日：2004-07-20

申请号：US09971820

申请日：2001-10-05

申请人： David B. Riggs ,  Rajarao Jammy ,  John Kim ,  Stephen M. Lucarini ,  George L. Mack ,  Christopher Parks

发明人： David B. Riggs ,  Rajarao Jammy ,  John Kim ,  Stephen M. Lucarini ,  George L. Mack ,  Christopher Parks

IPC分类号： B08B704

CPC分类号： H01L21/02046 ,  B08B7/00

摘要： A process for removing dopant ions from a semiconductor substrate includes exposing the substrate to a non-aqueous organic solvent in liquid and/or vapor form.

摘要翻译： 从半导体衬底去除掺杂剂离子的方法包括将衬底暴露于液体和/或蒸汽形式的非水有机溶剂中。

公开(公告)号：US06724088B1

公开(公告)日：2004-04-20

申请号：US09295132

申请日：1999-04-20

申请人： Rajarao Jammy ,  Jack A. Mandelman

发明人： Rajarao Jammy ,  Jack A. Mandelman

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L23/485 ,  H01L29/0895 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures such as source/drain contacts of improved reliability are enabled by the creation and use of quantum conductive barrier layers at the interface between the electrical contact and the shallow diffusion source/drain region. The quantum conductive layers are preferably nitrides or oxynitrides. The improved structure is preferably part of a transistor structure of an integrated circuit device. The contacts structures are especially useful for devices employing ultra-shallow junctions.

摘要翻译： 通过在电接触和浅扩散源极/漏极区之间的界面处产生和使用量子传导阻挡层，能够实现诸如具有改善的可靠性的源/漏触点的结构。 量子导电层优选为氮化物或氮氧化物。 改进的结构优选地是集成电路器件的晶体管结构的一部分。 触点结构对于采用超浅结的器件特别有用。

公开(公告)号：US06518119B2

公开(公告)日：2003-02-11

申请号：US09886065

申请日：2001-06-21

申请人： Jeffrey P. Gambino ,  Rajarao Jammy ,  Jack A. Mandelman ,  Carl J. Radens

发明人： Jeffrey P. Gambino ,  Rajarao Jammy ,  Jack A. Mandelman ,  Carl J. Radens

IPC分类号： H01L218242

CPC分类号： H01L27/10867 ,  H01L29/945

摘要： Reduced scale structures of improved reliability and/or increased composition options are enabled by the creation and use of intrinsically conductive recrystallization barrier layers. The intrinsically conductive layers are preferably used adjacent to conductive strap features in trench capacitors to act as recrystallization barriers.

摘要翻译： 通过产生和使用本征导电的再结晶阻挡层能够实现改进的可靠性和/或增加的组合选择的缩小结构。 本征导电层优选与沟槽电容器中的导电带特征相邻地用作再结晶屏障。

公开(公告)号：US06268299B1

公开(公告)日：2001-07-31

申请号：US09668988

申请日：2000-09-25

申请人： Rajarao Jammy ,  Johnathan E. Faltermeier ,  Keitaro Imai ,  Ryota Katsumata ,  Jean-Marc Rousseau ,  Viraj Y. Sardesai ,  Joseph F. Shepard, Jr.

发明人： Rajarao Jammy ,  Johnathan E. Faltermeier ,  Keitaro Imai ,  Ryota Katsumata ,  Jean-Marc Rousseau ,  Viraj Y. Sardesai ,  Joseph F. Shepard, Jr.

IPC分类号： H01L21318

CPC分类号： C23C14/0652 ,  H01L21/3185

摘要： A low-temperature process for forming a highly conformal barrier film during integrated circuit manufacture by low pressure chemical vapor deposition (LPCVD). The process includes the following steps. First, the process provides ammonia and a silicon-containing gas selected from the group consisting of silane, dichlorosilane, bistertiarybutylaminosilanc, hexachlorodisilane, and mixtures of those compositions. The ratio of the volume of ammonia to the volume of the silicon-containing gas is adjusted to yield silicon concentrations greater than 43 atomic percent in the resultant film. The process applies a deposition temperature of 550° C. to 720° C. The ammonia and the silicon-containing gas are reacted at the deposition temperature to form a silicon-rich nitride film less than 200 Å thick. Finally, the silicon nitride film is deposited by low pressure chemical vapor deposition.

摘要翻译： 在低压化学气相沉积（LPCVD）的集成电路制造过程中形成高保形阻挡膜的低温工艺。 该过程包括以下步骤。 首先，该方法提供氨和含硅气体，其选自硅烷，二氯硅烷，二丁基氨基硅烷，六氯二硅烷，以及这些组合物的混合物。 调节氨体积与含硅气体体积的比例，得到所得膜中硅浓度大于43原子百分比。 该方法将沉积温度为550℃至720℃。氨和含硅气体在沉积温度下反应，形成厚度小于200埃的富硅氮化物膜。 最后，通过低压化学气相沉积沉积氮化硅膜。

公开(公告)号：US20120318666A1

公开(公告)日：2012-12-20

申请号：US13561599

申请日：2012-07-30

申请人： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

发明人： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

IPC分类号： C25D19/00

CPC分类号： C25D5/18 ,  C25D5/024 ,  C25D17/001 ,  C25D17/002 ,  C25D17/005 ,  H01L21/2885 ,  H01L21/7624

摘要： An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane.

摘要翻译： 提供了一种用于在晶片的表面上沉积金属层的电镀设备和方法，其中所述设备和方法不需要将电极物理附接到晶片。 要镀覆的晶片的表面被定位成面对阳极，并且在晶片和电极之间设置电镀液以产生局部金属电镀。 晶片可以被定位成物理分离并且位于阳极和阴极之间，使得面向阳极的晶片的一侧包含阴极电解液，并且晶片的面向阴极的另一侧包含阳极电解液。 或者，阳极和阴极可以存在于同一电镀液中晶片的同一侧。 在一个实例中，阳极和阴极被半透膜隔开。

公开(公告)号：US20120142181A1

公开(公告)日：2012-06-07

申请号：US13369707

申请日：2012-02-09

申请人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/28

CPC分类号： H01L21/28079 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/6659

摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

摘要翻译： 制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。 第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。 平坦化层位于第二栅极材料层上。 平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。 也可以在第一栅极叠层上形成蚀刻停止层。 所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

公开(公告)号：US08158481B2

公开(公告)日：2012-04-17

申请号：US12683535

申请日：2010-01-07

申请人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

发明人： Tze-Chiang Chen ,  Meikei Ieong ,  Rajarao Jammy ,  Mukesh V. Khare ,  Chun-yung Sung ,  Richard Wise ,  Hongwen Yan ,  Ying Zhang

IPC分类号： H01L21/8234

CPC分类号： H01L21/28079 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/6659

摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.

摘要翻译： 制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。 第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。 平坦化层位于第二栅极材料层上。 平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。 也可以在第一栅极叠层上形成蚀刻停止层。 所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。